X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=16c8a925e7bc1d56635097ec8fe6071ad9522d18;hp=7400f18122c081fa7178968b2766494f57ab2c17;hb=410fab9ea8c6632da2e4967d960f66eecc7821ec;hpb=c87357a33f554e7e7c9e8f37cd15560c7e044cf4 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 7400f18122..16c8a925e7 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -30,25 +30,35 @@ #include "config.h" #endif +#include "breakpoints.h" #include "embeddedice.h" #include "target_request.h" -#include "arm7_9_common.h" +#include "etm.h" #include "time_support.h" #include "arm_simulator.h" +#include "algorithm.h" +#include "register.h" -int arm7_9_debug_entry(target_t *target); -int arm7_9_enable_sw_bkpts(struct target_s *target); +/** + * @file + * Hold common code supporting the ARM7 and ARM9 core generations. + * + * While the ARM core implementations evolved substantially during these + * two generations, they look quite similar from the JTAG perspective. + * Both have similar debug facilities, based on the same two scan chains + * providing access to the core and to an EmbeddedICE module. Both can + * support similar ETM and ETB modules, for tracing. And both expose + * what could be viewed as "ARM Classic", with multiple processor modes, + * shadowed registers, and support for the Thumb instruction set. + * + * Processor differences include things like presence or absence of MMU + * and cache, pipeline sizes, use of a modified Harvard Architecure + * (with separate instruction and data busses from the CPU), support + * for cpu clock gating during idle, and more. + */ -/* command handler forward declarations */ -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +static int arm7_9_debug_entry(struct target *target); /** * Clear watchpoints for an ARM7/9 target. @@ -56,11 +66,12 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char * @param arm7_9 Pointer to the common struct for an ARM7/9 target * @return JTAG error status after executing queue */ -static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) +static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9) { LOG_DEBUG("-"); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); + arm7_9->sw_breakpoint_count = 0; arm7_9->sw_breakpoints_added = 0; arm7_9->wp0_used = 0; arm7_9->wp1_used = arm7_9->wp1_used_default; @@ -76,7 +87,7 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) * @param arm7_9 Pointer to the common struct for an ARM7/9 target * @param breakpoint Pointer to the breakpoint to be used as a watchpoint */ -static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) +static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint) { if (!arm7_9->wp0_used) { @@ -94,7 +105,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) { LOG_ERROR("BUG: no hardware comparator available"); } - LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", breakpoint->unique_id, breakpoint->address, breakpoint->set ); @@ -107,7 +118,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) * @return Error codes if there is a problem finding a watchpoint or the result * of executing the JTAG queue */ -static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) +static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) { if (arm7_9->sw_breakpoints_added) { @@ -157,7 +168,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } - LOG_DEBUG("SW BP using hw wp: %d", + LOG_DEBUG("SW BP using hw wp: %d", arm7_9->sw_breakpoints_added ); return jtag_execute_queue(); @@ -169,47 +180,13 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) * @param target Pointer to an ARM7/9 target to setup * @return Result of clearing the watchpoints on the target */ -int arm7_9_setup(target_t *target) +int arm7_9_setup(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); return arm7_9_clear_watchpoints(arm7_9); } -/** - * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9 - * targets. A return of ERROR_OK signifies that the target is a valid target - * and that the pointers have been set properly. - * - * @param target Pointer to the target device to get the pointers from - * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5 - * targets - * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9 - * targets - * @return ERROR_OK if successful - */ -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } - - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - - return ERROR_OK; -} - /** * Set either a hardware or software breakpoint on an ARM7/9 target. The * breakpoint is set up even if it is already set. Some actions, e.g. reset, @@ -221,15 +198,15 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" , breakpoint->unique_id, - breakpoint->address ); + breakpoint->address, + breakpoint->type); if (target->state != TARGET_HALTED) { @@ -274,9 +251,6 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } else if (breakpoint->type == BKPT_SOFT) { - if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) - return retval; - /* did we already set this breakpoint? */ if (breakpoint->set) return ERROR_OK; @@ -329,6 +303,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } } + + if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) + return retval; + + arm7_9->sw_breakpoint_count++; + breakpoint->set = 1; } @@ -347,12 +327,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * queue. For software breakpoints, this will be the status of the * required memory reads and writes */ -int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; - - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, breakpoint->unique_id, @@ -366,7 +344,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { - LOG_DEBUG("BPID: %d Releasing hw wp: %d", + LOG_DEBUG("BPID: %d Releasing hw wp: %d", breakpoint->unique_id, breakpoint->set ); if (breakpoint->set == 1) @@ -415,6 +393,20 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return retval; } } + + if (--arm7_9->sw_breakpoint_count==0) + { + /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */ + if (arm7_9->sw_breakpoints_added == 1) + { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0); + } + else if (arm7_9->sw_breakpoints_added == 2) + { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0); + } + } + breakpoint->set = 0; } @@ -430,10 +422,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return An error status if there is a problem adding the breakpoint or the * result of setting the breakpoint */ -int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -481,11 +472,10 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return Error status if there was a problem unsetting the breakpoint or the * watchpoints could not be cleared */ -int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { @@ -518,11 +508,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return Error status if watchpoint set fails or the result of executing the * JTAG queue */ -int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int rw_mask = 1; uint32_t mask; @@ -590,11 +579,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @return Error status while trying to unset the watchpoint or the result of * executing the JTAG queue */ -int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -639,10 +627,9 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be added * @return Error status while trying to add the watchpoint */ -int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -673,11 +660,10 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be removed * @return Result of trying to unset the watchpoint */ -int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (watchpoint->set) { @@ -701,14 +687,12 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @return Error status if there is a timeout or a problem while executing the * JTAG queue */ -int arm7_9_execute_sys_speed(struct target_s *target) +int arm7_9_execute_sys_speed(struct target *target) { int retval; - - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -754,15 +738,14 @@ int arm7_9_execute_sys_speed(struct target_s *target) * @param target Pointer to the target to issue commands to * @return Always ERROR_OK */ -int arm7_9_execute_fast_sys_speed(struct target_s *target) +int arm7_9_execute_fast_sys_speed(struct target *target) { static int set = 0; static uint8_t check_value[4], check_mask[4]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -799,11 +782,10 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) * @param buffer Pointer to the buffer that will hold the data * @return The result of receiving data from the Embedded ICE unit */ -int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) +int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t *data; int retval = ERROR_OK; uint32_t i; @@ -828,20 +810,19 @@ int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) * target is running and the DCC control register has the W bit high, this will * execute the request on the target. * - * @param priv Void pointer expected to be a target_t pointer + * @param priv Void pointer expected to be a struct target pointer * @return ERROR_OK unless there are issues with the JTAG queue or when reading * from the Embedded ICE unit */ int arm7_9_handle_target_request(void *priv) { int retval = ERROR_OK; - target_t *target = priv; + struct target *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; if (!target->dbg_msg_enabled) return ERROR_OK; @@ -894,12 +875,11 @@ int arm7_9_handle_target_request(void *priv) * @param target Pointer to the ARM7/9 target to poll * @return ERROR_OK or an error status if a command fails */ -int arm7_9_poll(target_t *target) +int arm7_9_poll(struct target *target) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -939,7 +919,7 @@ int arm7_9_poll(target_t *target) if (check_pc) { - reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1); + struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1); uint32_t t=*((uint32_t *)reg->value); if (t != 0) { @@ -988,10 +968,10 @@ int arm7_9_poll(target_t *target) * @param target Pointer to an ARM7/9 target to assert reset on * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK */ -int arm7_9_assert_reset(target_t *target) +int arm7_9_assert_reset(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -1002,6 +982,24 @@ int arm7_9_assert_reset(target_t *target) return ERROR_FAIL; } + /* At this point trst has been asserted/deasserted once. We would + * like to program EmbeddedICE while SRST is asserted, instead of + * depending on SRST to leave that module alone. However, many CPUs + * gate the JTAG clock while SRST is asserted; or JTAG may need + * clock stability guarantees (adaptive clocking might help). + * + * So we assume JTAG access during SRST is off the menu unless it's + * been specifically enabled. + */ + bool srst_asserted = false; + + if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) + && (jtag_reset_config & RESET_SRST_NO_GATING)) + { + jtag_add_reset(0, 1); + srst_asserted = true; + } + if (target->reset_halt) { /* @@ -1034,7 +1032,7 @@ int arm7_9_assert_reset(target_t *target) if (jtag_reset_config & RESET_SRST_PULLS_TRST) { jtag_add_reset(1, 1); - } else + } else if (!srst_asserted) { jtag_add_reset(0, 1); } @@ -1062,7 +1060,7 @@ int arm7_9_assert_reset(target_t *target) * @param target Pointer to the target to have the reset deasserted * @return ERROR_OK or an error from polling or halting the target */ -int arm7_9_deassert_reset(target_t *target) +int arm7_9_deassert_reset(struct target *target) { int retval = ERROR_OK; LOG_DEBUG("target->state: %s", @@ -1102,11 +1100,10 @@ int arm7_9_deassert_reset(target_t *target) * @param target Pointer to the ARM7/9 target to have halt cleared * @return Always ERROR_OK */ -int arm7_9_clear_halt(target_t *target) +int arm7_9_clear_halt(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; /* we used DBGRQ only if we didn't come out of reset */ if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) @@ -1160,15 +1157,22 @@ int arm7_9_clear_halt(target_t *target) * @param target Pointer to the ARM7/9 target to be reset and halted by software * @return Error status if any of the commands fail, otherwise ERROR_OK */ -int arm7_9_soft_reset_halt(struct target_s *target) +int arm7_9_soft_reset_halt(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; int retval; + /* FIX!!! replace some of this code with tcl commands + * + * halt # the halt command is synchronous + * armv4_5 core_state arm + * + */ + if ((retval = target_halt(target)) != ERROR_OK) return retval; @@ -1238,9 +1242,6 @@ int arm7_9_soft_reset_halt(struct target_s *target) armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; - /* reset registers */ for (i = 0; i <= 14; i++) { @@ -1266,7 +1267,7 @@ int arm7_9_soft_reset_halt(struct target_s *target) * @param target Pointer to the ARM7/9 target to be halted * @return Always ERROR_OK */ -int arm7_9_halt(target_t *target) +int arm7_9_halt(struct target *target) { if (target->state == TARGET_RESET) { @@ -1274,9 +1275,8 @@ int arm7_9_halt(target_t *target) return ERROR_OK; } - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -1329,7 +1329,7 @@ int arm7_9_halt(target_t *target) * @param target Pointer to target that is entering debug mode * @return Error code if anything fails, otherwise ERROR_OK */ -int arm7_9_debug_entry(target_t *target) +static int arm7_9_debug_entry(struct target *target) { int i; uint32_t context[16]; @@ -1337,19 +1337,15 @@ int arm7_9_debug_entry(target_t *target) uint32_t r0_thumb, pc_thumb; uint32_t cpsr; int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; #ifdef _DEBUG_ARM7_9_ LOG_DEBUG("-"); #endif - if (arm7_9->pre_debug_entry) - arm7_9->pre_debug_entry(target); - /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS * ensure that DBGRQ is cleared */ @@ -1414,14 +1410,15 @@ int arm7_9_debug_entry(target_t *target) armv4_5->core_mode = cpsr & 0x1f; - if (armv4_5_mode_to_number(armv4_5->core_mode) == -1) + if (!is_arm_mode(armv4_5->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } - LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]); + LOG_DEBUG("target entered debug state in %s mode", + arm_mode_name(armv4_5->core_mode)); if (armv4_5->core_state == ARMV4_5_STATE_THUMB) { @@ -1439,9 +1436,6 @@ int arm7_9_debug_entry(target_t *target) else context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; - for (i = 0; i <= 15; i++) { LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); @@ -1452,9 +1446,6 @@ int arm7_9_debug_entry(target_t *target) LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) - return ERROR_FAIL; - /* exceptions other than USR & SYS have a saved program status register */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { @@ -1491,12 +1482,12 @@ int arm7_9_debug_entry(target_t *target) * @return Error if the target is not halted, has an invalid core mode, or if * the JTAG queue fails to execute */ -int arm7_9_full_context(target_t *target) +int arm7_9_full_context(struct target *target) { int i; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; LOG_DEBUG("-"); @@ -1506,7 +1497,7 @@ int arm7_9_full_context(target_t *target) return ERROR_TARGET_NOT_HALTED; } - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) @@ -1584,12 +1575,12 @@ int arm7_9_full_context(target_t *target) * @return Error status if the target is not halted or the core mode in the * armv4_5 struct is invalid. */ -int arm7_9_restore_context(target_t *target) +int arm7_9_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *reg; - armv4_5_core_reg_t *reg_arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct reg *reg; + struct armv4_5_core_reg *reg_arch_info; enum armv4_5_mode current_mode = armv4_5->core_mode; int i, j; int dirty; @@ -1606,7 +1597,7 @@ int arm7_9_restore_context(target_t *target) if (arm7_9->pre_restore_context) arm7_9->pre_restore_context(target); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) @@ -1614,7 +1605,8 @@ int arm7_9_restore_context(target_t *target) */ for (i = 0; i < 6; i++) { - LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]); + LOG_DEBUG("examining %s mode", + arm_mode_name(armv4_5->core_mode)); dirty = 0; mode_change = 0; /* check if there are dirty registers in the current mode @@ -1676,7 +1668,10 @@ int arm7_9_restore_context(target_t *target) num_regs++; reg->dirty = 0; reg->valid = 1; - LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]); + LOG_DEBUG("writing register %i mode %s " + "with value 0x%8.8" PRIx32, j, + arm_mode_name(armv4_5->core_mode), + regs[j]); } } @@ -1734,11 +1729,10 @@ int arm7_9_restore_context(target_t *target) * @param target Pointer to the ARM7/9 target to be restarted * @return Result of executing the JTAG queue */ -int arm7_9_restart_core(struct target_s *target) +int arm7_9_restart_core(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -1758,9 +1752,9 @@ int arm7_9_restart_core(struct target_s *target) * * @param target Pointer to the ARM7/9 target to enable watchpoints on */ -void arm7_9_enable_watchpoints(struct target_s *target) +void arm7_9_enable_watchpoints(struct target *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; while (watchpoint) { @@ -1776,9 +1770,9 @@ void arm7_9_enable_watchpoints(struct target_s *target) * * @param target Pointer to the ARM7/9 target to enable breakpoints on */ -void arm7_9_enable_breakpoints(struct target_s *target) +void arm7_9_enable_breakpoints(struct target *target) { - breakpoint_t *breakpoint = target->breakpoints; + struct breakpoint *breakpoint = target->breakpoints; /* set any pending breakpoints */ while (breakpoint) @@ -1788,12 +1782,12 @@ void arm7_9_enable_breakpoints(struct target_s *target) } } -int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - breakpoint_t *breakpoint = target->breakpoints; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct breakpoint *breakpoint = target->breakpoints; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; LOG_DEBUG("-"); @@ -1948,11 +1942,10 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha return ERROR_OK; } -void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) +void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1986,10 +1979,9 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) } } -void arm7_9_disable_eice_step(target_t *target) +void arm7_9_disable_eice_step(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); @@ -2002,11 +1994,11 @@ void arm7_9_disable_eice_step(target_t *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]); } -int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - breakpoint_t *breakpoint = NULL; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct breakpoint *breakpoint = NULL; int err, retval; if (target->state != TARGET_HALTED) @@ -2095,18 +2087,18 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand return err; } -int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) +int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode) { uint32_t* reg_p[16]; uint32_t value; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2136,7 +2128,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod /* read a program status register * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; arm7_9->read_xpsr(target, &value, spsr); @@ -2161,16 +2153,16 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod return ERROR_OK; } -int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) +int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode, uint32_t value) { uint32_t reg[16]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2199,7 +2191,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo /* write a program status register * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; /* if we're writing the CPSR, mask the T bit */ @@ -2222,11 +2214,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo return jtag_execute_queue(); } -int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t reg[16]; uint32_t num_accesses = 0; int thisrun_accesses; @@ -2373,7 +2364,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, break; } - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) @@ -2398,11 +2389,11 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, return ERROR_OK; } -int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; uint32_t num_accesses = 0; @@ -2556,7 +2547,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1); embeddedice_store_reg(dbg_ctrl); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) @@ -2584,11 +2575,10 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size static int dcc_count; static uint8_t *dcc_buffer; -static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; @@ -2603,9 +2593,9 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); buffer += 4; - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; - jtag_tap_t *tap; + struct jtag_tap *tap; tap = ice_reg->jtag_info->tap; embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); @@ -2631,17 +2621,29 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i static const uint32_t dcc_code[] = { - /* MRC TST BNE MRC STR B */ - 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 + /* r0 == input, points to memory buffer + * r1 == scratch + */ + + /* spin until DCC control (c0) reports data arrived */ + 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */ + 0xe3110001, /* tst r1, #1 */ + 0x0afffffc, /* bne w */ + + /* read word from DCC (c1), write to memory */ + 0xee111e10, /* mrc p14, #0, r1, c1, c0 */ + 0xe4801004, /* str r1, [r0], #4 */ + + /* repeat */ + 0xeafffff9 /* b w */ }; -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); +int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)); -int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) +int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int i; if (!arm7_9->dcc_downloads) @@ -2672,8 +2674,8 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, } } - armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[1]; + struct armv4_5_algorithm armv4_5_info; + struct reg_param reg_params[1]; armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2703,207 +2705,70 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, return retval; } -int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +/** + * Perform per-target setup that requires JTAG access. + */ +int arm7_9_examine(struct target *target) { - working_area_t *crc_algorithm; - armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[2]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval; - uint32_t arm7_9_crc_code[] = { - 0xE1A02000, /* mov r2, r0 */ - 0xE3E00000, /* mov r0, #0xffffffff */ - 0xE1A03001, /* mov r3, r1 */ - 0xE3A04000, /* mov r4, #0 */ - 0xEA00000B, /* b ncomp */ - /* nbyte: */ - 0xE7D21004, /* ldrb r1, [r2, r4] */ - 0xE59F7030, /* ldr r7, CRC32XOR */ - 0xE0200C01, /* eor r0, r0, r1, asl 24 */ - 0xE3A05000, /* mov r5, #0 */ - /* loop: */ - 0xE3500000, /* cmp r0, #0 */ - 0xE1A06080, /* mov r6, r0, asl #1 */ - 0xE2855001, /* add r5, r5, #1 */ - 0xE1A00006, /* mov r0, r6 */ - 0xB0260007, /* eorlt r0, r6, r7 */ - 0xE3550008, /* cmp r5, #8 */ - 0x1AFFFFF8, /* bne loop */ - 0xE2844001, /* add r4, r4, #1 */ - /* ncomp: */ - 0xE1540003, /* cmp r4, r3 */ - 0x1AFFFFF1, /* bne nbyte */ - /* end: */ - 0xEAFFFFFE, /* b end */ - 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */ - }; - - uint32_t i; - - if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK) - { - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++) - { - if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) - { - return retval; - } - } - - armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; + if (!target_was_examined(target)) { + struct reg_cache *t, **cache_p; - init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + t = embeddedice_build_reg_cache(target, arm7_9); + if (t == NULL) + return ERROR_FAIL; - buf_set_u32(reg_params[0].value, 0, 32, address); - buf_set_u32(reg_params[1].value, 0, 32, count); + cache_p = register_get_last_cache_p(&target->reg_cache); + (*cache_p) = t; + arm7_9->eice_cache = (*cache_p); - if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK) - { - LOG_ERROR("error executing arm7_9 crc algorithm"); - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - target_free_working_area(target, crc_algorithm); - return retval; - } - - *checksum = buf_get_u32(reg_params[0].value, 0, 32); - - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); + if (arm7_9->armv4_5_common.etm) + (*cache_p)->next = etm_build_reg_cache(target, + &arm7_9->jtag_info, + arm7_9->armv4_5_common.etm); - target_free_working_area(target, crc_algorithm); - - return ERROR_OK; -} - -int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) -{ - working_area_t *erase_check_algorithm; - reg_param_t reg_params[3]; - armv4_5_algorithm_t armv4_5_info; - int retval; - uint32_t i; - - uint32_t erase_check_code[] = - { - /* loop: */ - 0xe4d03001, /* ldrb r3, [r0], #1 */ - 0xe0022003, /* and r2, r2, r3 */ - 0xe2511001, /* subs r1, r1, #1 */ - 0x1afffffb, /* bne loop */ - /* end: */ - 0xeafffffe /* b end */ - }; - - /* make sure we have a working area */ - if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK) - { - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + target_set_examined(target); } - /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint32_t)); i++) - if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i])) != ERROR_OK) - { - return retval; - } - - armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV4_5_MODE_SVC; - armv4_5_info.core_state = ARMV4_5_STATE_ARM; - - init_reg_param(®_params[0], "r0", 32, PARAM_OUT); - buf_set_u32(reg_params[0].value, 0, 32, address); - - init_reg_param(®_params[1], "r1", 32, PARAM_OUT); - buf_set_u32(reg_params[1].value, 0, 32, count); - - init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); - buf_set_u32(reg_params[2].value, 0, 32, 0xff); - - if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK) - { - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - target_free_working_area(target, erase_check_algorithm); - return 0; - } - - *blank = buf_get_u32(reg_params[2].value, 0, 32); - - destroy_reg_param(®_params[0]); - destroy_reg_param(®_params[1]); - destroy_reg_param(®_params[2]); - - target_free_working_area(target, erase_check_algorithm); - - return ERROR_OK; + retval = embeddedice_setup(target); + if (retval == ERROR_OK) + retval = arm7_9_setup(target); + if (retval == ERROR_OK && arm7_9->armv4_5_common.etm) + retval = etm_setup(target); + return retval; } -int arm7_9_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm7_9_cmd; - - arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); - register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); - - register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, - COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); - register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); - register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, - COMMAND_ANY, "use DCC downloads for larger memory writes "); - - armv4_5_register_commands(cmd_ctx); - - etm_register_commands(cmd_ctx); - - return ERROR_OK; -} - -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_command) { uint32_t value; int spsr; int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + command_print(CMD_CTX, "can't write registers while running"); + return ERROR_FAIL; } - if (argc < 2) + if (CMD_ARGC < 2) { - command_print(cmd_ctx, "usage: write_xpsr "); - return ERROR_OK; + command_print(CMD_CTX, "usage: write_xpsr "); + return ERROR_FAIL; } - value = strtoul(args[0], NULL, 0); - spsr = strtol(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], spsr); /* if we're writing the CPSR, mask the T bit */ if (!spsr) @@ -2919,37 +2784,36 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command) { uint32_t value; int rotate; int spsr; int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + command_print(CMD_CTX, "can't write registers while running"); + return ERROR_FAIL; } - if (argc < 3) + if (CMD_ARGC < 3) { - command_print(cmd_ctx, "usage: write_xpsr_im8 "); - return ERROR_OK; + command_print(CMD_CTX, "usage: write_xpsr_im8 "); + return ERROR_FAIL; } - value = strtoul(args[0], NULL, 0); - rotate = strtol(args[1], NULL, 0); - spsr = strtol(args[2], NULL, 0); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], rotate); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], spsr); arm7_9->write_xpsr_im8(target, value, rotate, spsr); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -2961,188 +2825,159 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) { uint32_t value; uint32_t mode; int num; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "can't write registers while running"); - return ERROR_OK; + command_print(CMD_CTX, "can't write registers while running"); + return ERROR_FAIL; } - if (argc < 3) + if (CMD_ARGC < 3) { - command_print(cmd_ctx, "usage: write_core_reg "); - return ERROR_OK; + command_print(CMD_CTX, "usage: write_core_reg "); + return ERROR_FAIL; } - num = strtol(args[0], NULL, 0); - mode = strtoul(args[1], NULL, 0); - value = strtoul(args[2], NULL, 0); + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], num); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], mode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); return arm7_9_write_core_reg(target, num, mode, value); } -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } - if (argc > 0) - { - if (strcmp("enable", args[0]) == 0) - { - arm7_9->use_dbgrq = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - arm7_9->use_dbgrq = 0; - } - else - { - command_print(cmd_ctx, "usage: arm7_9 dbgrq "); - } - } + if (CMD_ARGC > 0) + COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq); - command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled"); + command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled"); return ERROR_OK; } -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } - if (argc > 0) - { - if (strcmp("enable", args[0]) == 0) - { - arm7_9->fast_memory_access = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - arm7_9->fast_memory_access = 0; - } - else - { - command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); - } - } + if (CMD_ARGC > 0) + COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access); - command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled"); + command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled"); return ERROR_OK; } -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct target *target = get_current_target(CMD_CTX); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) + if (!is_arm7_9(arm7_9)) { - command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target"); - return ERROR_OK; + command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + return ERROR_TARGET_INVALID; } - if (argc > 0) - { - if (strcmp("enable", args[0]) == 0) - { - arm7_9->dcc_downloads = 1; - } - else if (strcmp("disable", args[0]) == 0) - { - arm7_9->dcc_downloads = 0; - } - else - { - command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); - } - } + if (CMD_ARGC > 0) + COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads); - command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled"); + command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled"); return ERROR_OK; } -int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) +int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) - { return retval; - } - arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ - arm7_9->wp_available_max = 2; - arm7_9->sw_breakpoints_added = 0; - arm7_9->breakpoint_count = 0; - arm7_9->wp0_used = 0; - arm7_9->wp1_used = 0; - arm7_9->wp1_used_default = 0; - arm7_9->use_dbgrq = 0; - - arm7_9->etm_ctx = NULL; - arm7_9->has_single_step = 0; - arm7_9->has_monitor_mode = 0; - arm7_9->has_vector_catch = 0; + /* caller must have allocated via calloc(), so everything's zeroed */ - arm7_9->debug_entry_from_reset = 0; - - arm7_9->dcc_working_area = NULL; + arm7_9->wp_available_max = 2; arm7_9->fast_memory_access = fast_and_dangerous; arm7_9->dcc_downloads = fast_and_dangerous; - arm7_9->need_bypass_before_restart = 0; - armv4_5->arch_info = arm7_9; armv4_5->read_core_reg = arm7_9_read_core_reg; armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) - { return retval; - } - if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) - { - return retval; - } + return target_register_timer_callback(arm7_9_handle_target_request, + 1, 1, target); +} + +int arm7_9_register_commands(struct command_context *cmd_ctx) +{ + struct command *arm7_9_cmd; + + arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", + NULL, COMMAND_ANY, "arm7/9 specific commands"); + + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", + handle_arm7_9_write_xpsr_command, COMMAND_EXEC, + "write program status register "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", + handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, + "write program status register " + "<8bit immediate> "); + + register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", + handle_arm7_9_write_core_reg_command, COMMAND_EXEC, + "write core register "); + + register_command(cmd_ctx, arm7_9_cmd, "dbgrq", + handle_arm7_9_dbgrq_command, COMMAND_ANY, + "use EmbeddedICE dbgrq instead of breakpoint " + "for target halt requests "); + register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", + handle_arm7_9_fast_memory_access_command, COMMAND_ANY, + "use fast memory accesses instead of slower " + "but potentially safer accesses "); + register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", + handle_arm7_9_dcc_downloads_command, COMMAND_ANY, + "use DCC downloads for larger memory writes "); + + armv4_5_register_commands(cmd_ctx); + + etm_register_commands(cmd_ctx); return ERROR_OK; }