X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=0289d3cbf890e6fede288bd2817610b88368adc1;hp=2b2787476ae84d6da0cf41c3f486ee54faf65b16;hb=b1de5eb9a074b362e953e857c42cac9a9b18b2a3;hpb=3813fda44adcea486b7308423a699f63d79273ee diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 2b2787476a..0289d3cbf8 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -38,17 +38,6 @@ int arm7_9_debug_entry(target_t *target); -int arm7_9_enable_sw_bkpts(struct target_s *target); - -/* command handler forward declarations */ -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /** * Clear watchpoints for an ARM7/9 target. @@ -58,8 +47,10 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char */ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { + LOG_DEBUG("-"); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); + arm7_9->sw_breakpoint_count = 0; arm7_9->sw_breakpoints_added = 0; arm7_9->wp0_used = 0; arm7_9->wp1_used = arm7_9->wp1_used_default; @@ -93,6 +84,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) { LOG_ERROR("BUG: no hardware comparator available"); } + LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + breakpoint->unique_id, + breakpoint->address, + breakpoint->set ); } /** @@ -118,11 +113,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { - arm7_9->sw_breakpoints_added=1; + arm7_9->sw_breakpoints_added = 1; arm7_9->wp0_used = 3; } else if (!arm7_9->wp1_used) { - arm7_9->sw_breakpoints_added=2; + arm7_9->sw_breakpoints_added = 2; arm7_9->wp1_used = 3; } else @@ -152,6 +147,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } + LOG_DEBUG("SW BP using hw wp: %d", + arm7_9->sw_breakpoints_added ); return jtag_execute_queue(); } @@ -164,8 +161,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) */ int arm7_9_setup(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); return arm7_9_clear_watchpoints(arm7_9); } @@ -184,18 +180,18 @@ int arm7_9_setup(target_t *target) */ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + /* FIXME stop using this routine; just target_to_arm7_9() and + * verify the resulting pointer using a replacement routine + * that emits a usage message. + */ if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } + return ERROR_TARGET_INVALID; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } + return ERROR_TARGET_INVALID; *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; @@ -216,9 +212,13 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm */ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - int retval=ERROR_OK; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + int retval = ERROR_OK; + + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" , + breakpoint->unique_id, + breakpoint->address, + breakpoint->type); if (target->state != TARGET_HALTED) { @@ -259,13 +259,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } - retval=jtag_execute_queue(); + retval = jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { - if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) - return retval; - /* did we already set this breakpoint? */ if (breakpoint->set) return ERROR_OK; @@ -318,6 +315,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } } + + if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) + return retval; + + arm7_9->sw_breakpoint_count++; + breakpoint->set = 1; } @@ -339,9 +342,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + breakpoint->unique_id, + breakpoint->address ); if (!breakpoint->set) { @@ -351,6 +356,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { + LOG_DEBUG("BPID: %d Releasing hw wp: %d", + breakpoint->unique_id, + breakpoint->set ); if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -397,6 +405,20 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return retval; } } + + if (--arm7_9->sw_breakpoint_count==0) + { + /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */ + if (arm7_9->sw_breakpoints_added == 1) + { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0); + } + else if (arm7_9->sw_breakpoints_added == 2) + { + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0); + } + } + breakpoint->set = 0; } @@ -414,8 +436,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) */ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -466,8 +487,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { @@ -503,8 +523,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); int rw_mask = 1; uint32_t mask; @@ -526,7 +545,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask); - if ( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); @@ -543,7 +562,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask); - if ( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); @@ -575,8 +594,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -623,8 +641,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) */ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -658,8 +675,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); if (watchpoint->set) { @@ -686,9 +702,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_execute_sys_speed(struct target_s *target) { int retval; - - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; @@ -700,9 +714,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -738,11 +752,10 @@ int arm7_9_execute_sys_speed(struct target_s *target) */ int arm7_9_execute_fast_sys_speed(struct target_s *target) { - static int set=0; + static int set = 0; static uint8_t check_value[4], check_mask[4]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; @@ -764,7 +777,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) * */ buf_set_u32(check_value, 0, 32, 0x9); buf_set_u32(check_mask, 0, 32, 0x9); - set=1; + set = 1; } /* read debug status register */ @@ -783,8 +796,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) */ int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); arm_jtag_t *jtag_info = &arm7_9->jtag_info; uint32_t *data; int retval = ERROR_OK; @@ -820,8 +832,7 @@ int arm7_9_handle_target_request(void *priv) target_t *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; @@ -862,11 +873,11 @@ int arm7_9_handle_target_request(void *priv) * what happens: * * - * - * - * - * - * + * + * + * + * + * *
StateAction
TARGET_RUNNING | TARGET_RESETEnters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWNWarning is logged
TARGET_DEBUG_RUNNINGEnters debug mode
TARGET_HALTEDNothing
State Action
TARGET_RUNNING | TARGET_RESET Enters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWN Warning is logged
TARGET_DEBUG_RUNNING Enters debug mode
TARGET_HALTED Nothing
* * If the target does not end up in the halted state, a warning is produced. If @@ -879,8 +890,7 @@ int arm7_9_handle_target_request(void *priv) int arm7_9_poll(target_t *target) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* read debug status register */ @@ -895,12 +905,13 @@ int arm7_9_poll(target_t *target) /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/ if (target->state == TARGET_UNKNOWN) { + /* Starting OpenOCD with target in debug-halt */ target->state = TARGET_RUNNING; - LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target."); + LOG_DEBUG("DBGACK already set during server startup."); } if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - int check_pc=0; + int check_pc = 0; if (target->state == TARGET_RESET) { if (target->reset_halt) @@ -971,10 +982,10 @@ int arm7_9_poll(target_t *target) */ int arm7_9_assert_reset(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (!(jtag_reset_config & RESET_HAS_SRST)) @@ -983,6 +994,24 @@ int arm7_9_assert_reset(target_t *target) return ERROR_FAIL; } + /* At this point trst has been asserted/deasserted once. We would + * like to program EmbeddedICE while SRST is asserted, instead of + * depending on SRST to leave that module alone. However, many CPUs + * gate the JTAG clock while SRST is asserted; or JTAG may need + * clock stability guarantees (adaptive clocking might help). + * + * So we assume JTAG access during SRST is off the menu unless it's + * been specifically enabled. + */ + bool srst_asserted = false; + + if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) + && (jtag_reset_config & RESET_SRST_NO_GATING)) + { + jtag_add_reset(0, 1); + srst_asserted = true; + } + if (target->reset_halt) { /* @@ -996,6 +1025,9 @@ int arm7_9_assert_reset(target_t *target) { /* program vector catch register to catch reset vector */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); + + /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */ + jtag_add_runtest(1, jtag_get_end_state()); } else { @@ -1012,7 +1044,7 @@ int arm7_9_assert_reset(target_t *target) if (jtag_reset_config & RESET_SRST_PULLS_TRST) { jtag_add_reset(1, 1); - } else + } else if (!srst_asserted) { jtag_add_reset(0, 1); } @@ -1042,9 +1074,9 @@ int arm7_9_assert_reset(target_t *target) */ int arm7_9_deassert_reset(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -1057,12 +1089,12 @@ int arm7_9_deassert_reset(target_t *target) if ((retval = target_examine_one(target)) != ERROR_OK) return retval; - if ((retval=target_poll(target)) != ERROR_OK) + if ((retval = target_poll(target)) != ERROR_OK) { return retval; } - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } @@ -1082,8 +1114,7 @@ int arm7_9_deassert_reset(target_t *target) */ int arm7_9_clear_halt(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; /* we used DBGRQ only if we didn't come out of reset */ @@ -1140,24 +1171,31 @@ int arm7_9_clear_halt(target_t *target) */ int arm7_9_soft_reset_halt(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; int retval; - if ((retval=target_halt(target)) != ERROR_OK) + /* FIX!!! replace some of this code with tcl commands + * + * halt # the halt command is synchronous + * armv4_5 core_state arm + * + */ + + if ((retval = target_halt(target)) != ERROR_OK) return retval; - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; if (debug_level >= 3) { @@ -1252,12 +1290,11 @@ int arm7_9_halt(target_t *target) return ERROR_OK; } - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1315,9 +1352,8 @@ int arm7_9_debug_entry(target_t *target) uint32_t r0_thumb, pc_thumb; uint32_t cpsr; int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -1325,9 +1361,6 @@ int arm7_9_debug_entry(target_t *target) LOG_DEBUG("-"); #endif - if (arm7_9->pre_debug_entry) - arm7_9->pre_debug_entry(target); - /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS * ensure that DBGRQ is cleared */ @@ -1412,23 +1445,15 @@ int arm7_9_debug_entry(target_t *target) context[15] -= 3 * 4; } - if ((target->debug_reason == DBG_REASON_BREAKPOINT) - || (target->debug_reason == DBG_REASON_SINGLESTEP) - || (target->debug_reason == DBG_REASON_WATCHPOINT) - || (target->debug_reason == DBG_REASON_WPTANDBKPT) - || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0))) + if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); - else if (target->debug_reason == DBG_REASON_DBGRQ) - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); else - { - LOG_ERROR("unknown debug reason: %i", target->debug_reason); - } + context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= 15; i++) + for (i = 0; i <= 15; i++) { LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); @@ -1481,8 +1506,8 @@ int arm7_9_full_context(target_t *target) { int i; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; LOG_DEBUG("-"); @@ -1572,8 +1597,8 @@ int arm7_9_full_context(target_t *target) */ int arm7_9_restore_context(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *reg; armv4_5_core_reg_t *reg_arch_info; enum armv4_5_mode current_mode = armv4_5->core_mode; @@ -1722,8 +1747,7 @@ int arm7_9_restore_context(target_t *target) */ int arm7_9_restart_core(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); arm_jtag_t *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ @@ -1776,8 +1800,8 @@ void arm7_9_enable_breakpoints(struct target_s *target) int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; @@ -1807,7 +1831,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha { if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { return retval; @@ -1819,7 +1843,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } @@ -1936,9 +1960,8 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -1951,7 +1974,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); @@ -1974,8 +1997,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) void arm7_9_disable_eice_step(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); @@ -1990,8 +2012,8 @@ void arm7_9_disable_eice_step(target_t *target) int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; breakpoint_t *breakpoint = NULL; int err, retval; @@ -2024,7 +2046,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand { uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); + LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } @@ -2086,8 +2108,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod uint32_t* reg_p[16]; uint32_t value; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; @@ -2150,8 +2172,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) { uint32_t reg[16]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; @@ -2210,9 +2232,8 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t reg[16]; uint32_t num_accesses = 0; int thisrun_accesses; @@ -2240,7 +2261,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); - int j=0; + int j = 0; switch (size) { @@ -2362,7 +2383,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2386,8 +2407,8 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; @@ -2545,7 +2566,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i <= last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2573,16 +2594,15 @@ static uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; - int little=target->endianness == TARGET_LITTLE_ENDIAN; - int count=dcc_count; - uint8_t *buffer=dcc_buffer; - if (count>2) + int little = target->endianness == TARGET_LITTLE_ENDIAN; + int count = dcc_count; + uint8_t *buffer = dcc_buffer; + if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the * core function repeated. */ @@ -2591,7 +2611,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; - jtag_tap_t *tap; + struct jtag_tap *tap; tap = ice_reg->jtag_info->tap; embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); @@ -2617,17 +2637,29 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i static const uint32_t dcc_code[] = { - /* MRC TST BNE MRC STR B */ - 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 + /* r0 == input, points to memory buffer + * r1 == scratch + */ + + /* spin until DCC control (c0) reports data arrived */ + 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */ + 0xe3110001, /* tst r1, #1 */ + 0x0afffffc, /* bne w */ + + /* read word from DCC (c1), write to memory */ + 0xee111e10, /* mrc p14, #0, r1, c1, c0 */ + 0xe4801004, /* str r1, [r0], #4 */ + + /* repeat */ + 0xeafffff9 /* b w */ }; -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); int i; if (!arm7_9->dcc_downloads) @@ -2659,7 +2691,7 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, } armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[1]; + struct reg_param reg_params[1]; armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2669,18 +2701,18 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, buf_set_u32(reg_params[0].value, 0, 32, address); - dcc_count=count; - dcc_buffer=buffer; + dcc_count = count; + dcc_buffer = buffer; retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, - arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); if (retval == ERROR_OK) { - uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32); - if (endaddress != (address+count*4)) + uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress != (address + count*4)) { - LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress); - retval=ERROR_FAIL; + LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress); + retval = ERROR_FAIL; } } @@ -2693,10 +2725,10 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c { working_area_t *crc_algorithm; armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[2]; + struct reg_param reg_params[2]; int retval; - uint32_t arm7_9_crc_code[] = { + static const uint32_t arm7_9_crc_code[] = { 0xE1A02000, /* mov r2, r0 */ 0xE3E00000, /* mov r0, #0xffffffff */ 0xE1A03001, /* mov r3, r1 */ @@ -2734,7 +2766,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++) { - if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) + if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) { return retval; } @@ -2750,8 +2782,11 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c buf_set_u32(reg_params[0].value, 0, 32, address); buf_set_u32(reg_params[1].value, 0, 32, count); + /* 20 second timeout/megabyte */ + int timeout = 20000 * (1 + (count / (1024*1024))); + if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, - crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK) + crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), timeout, &armv4_5_info)) != ERROR_OK) { LOG_ERROR("error executing arm7_9 crc algorithm"); destroy_reg_param(®_params[0]); @@ -2773,20 +2808,20 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) { working_area_t *erase_check_algorithm; - reg_param_t reg_params[3]; + struct reg_param reg_params[3]; armv4_5_algorithm_t armv4_5_info; int retval; uint32_t i; - uint32_t erase_check_code[] = + static const uint32_t erase_check_code[] = { - /* loop: */ - 0xe4d03001, /* ldrb r3, [r0], #1 */ - 0xe0022003, /* and r2, r2, r3 */ - 0xe2511001, /* subs r1, r1, #1 */ - 0x1afffffb, /* bne loop */ - /* end: */ - 0xeafffffe /* b end */ + /* loop: */ + 0xe4d03001, /* ldrb r3, [r0], #1 */ + 0xe0022003, /* and r2, r2, r3 */ + 0xe2511001, /* subs r1, r1, #1 */ + 0x1afffffb, /* bne loop */ + /* end: */ + 0xeafffffe /* b end */ }; /* make sure we have a working area */ @@ -2836,32 +2871,7 @@ int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_ return ERROR_OK; } -int arm7_9_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm7_9_cmd; - - arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); - - register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); - - register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, - COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); - register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); - register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, - COMMAND_ANY, "use DCC downloads for larger memory writes "); - - armv4_5_register_commands(cmd_ctx); - - etm_register_commands(cmd_ctx); - - return ERROR_OK; -} - -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_command) { uint32_t value; int spsr; @@ -2884,12 +2894,12 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm if (argc < 2) { - command_print(cmd_ctx, "usage: write_xpsr "); + command_print(cmd_ctx, "usage: write_xpsr "); return ERROR_OK; } - value = strtoul(args[0], NULL, 0); - spsr = strtol(args[1], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[0], value); + COMMAND_PARSE_NUMBER(int, args[1], spsr); /* if we're writing the CPSR, mask the T bit */ if (!spsr) @@ -2905,7 +2915,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command) { uint32_t value; int rotate; @@ -2929,13 +2939,13 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char if (argc < 3) { - command_print(cmd_ctx, "usage: write_xpsr_im8 "); + command_print(cmd_ctx, "usage: write_xpsr_im8 "); return ERROR_OK; } - value = strtoul(args[0], NULL, 0); - rotate = strtol(args[1], NULL, 0); - spsr = strtol(args[2], NULL, 0); + COMMAND_PARSE_NUMBER(u32, args[0], value); + COMMAND_PARSE_NUMBER(int, args[1], rotate); + COMMAND_PARSE_NUMBER(int, args[2], spsr); arm7_9->write_xpsr_im8(target, value, rotate, spsr); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -2947,7 +2957,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) { uint32_t value; uint32_t mode; @@ -2974,14 +2984,14 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } - num = strtol(args[0], NULL, 0); - mode = strtoul(args[1], NULL, 0); - value = strtoul(args[2], NULL, 0); + COMMAND_PARSE_NUMBER(int, args[0], num); + COMMAND_PARSE_NUMBER(u32, args[1], mode); + COMMAND_PARSE_NUMBER(u32, args[2], value); return arm7_9_write_core_reg(target, num, mode, value); } -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3005,7 +3015,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch } else { - command_print(cmd_ctx, "usage: arm7_9 dbgrq "); + command_print(cmd_ctx, "usage: arm7_9 dbgrq "); } } @@ -3014,7 +3024,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch return ERROR_OK; } -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3038,7 +3048,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, } else { - command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); + command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); } } @@ -3047,7 +3057,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -3071,7 +3081,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char } else { - command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); + command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); } } @@ -3088,47 +3098,61 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) - { return retval; - } - arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ - arm7_9->wp_available_max = 2; - arm7_9->sw_breakpoints_added = 0; - arm7_9->breakpoint_count = 0; - arm7_9->wp0_used = 0; - arm7_9->wp1_used = 0; - arm7_9->wp1_used_default = 0; - arm7_9->use_dbgrq = 0; + /* caller must have allocated via calloc(), so everything's zeroed */ - arm7_9->etm_ctx = NULL; - arm7_9->has_single_step = 0; - arm7_9->has_monitor_mode = 0; - arm7_9->has_vector_catch = 0; - - arm7_9->debug_entry_from_reset = 0; - - arm7_9->dcc_working_area = NULL; + arm7_9->wp_available_max = 2; arm7_9->fast_memory_access = fast_and_dangerous; arm7_9->dcc_downloads = fast_and_dangerous; - arm7_9->need_bypass_before_restart = 0; - armv4_5->arch_info = arm7_9; armv4_5->read_core_reg = arm7_9_read_core_reg; armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) - { return retval; - } - if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) - { - return retval; - } + return target_register_timer_callback(arm7_9_handle_target_request, + 1, 1, target); +} + +int arm7_9_register_commands(struct command_context_s *cmd_ctx) +{ + command_t *arm7_9_cmd; + + arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", + NULL, COMMAND_ANY, "arm7/9 specific commands"); + + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", + handle_arm7_9_write_xpsr_command, COMMAND_EXEC, + "write program status register "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", + handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, + "write program status register " + "<8bit immediate> "); + + register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", + handle_arm7_9_write_core_reg_command, COMMAND_EXEC, + "write core register "); + + register_command(cmd_ctx, arm7_9_cmd, "dbgrq", + handle_arm7_9_dbgrq_command, COMMAND_ANY, + "use EmbeddedICE dbgrq instead of breakpoint " + "for target halt requests "); + register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", + handle_arm7_9_fast_memory_access_command, COMMAND_ANY, + "use fast memory accesses instead of slower " + "but potentially safer accesses "); + register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", + handle_arm7_9_dcc_downloads_command, COMMAND_ANY, + "use DCC downloads for larger memory writes "); + + armv4_5_register_commands(cmd_ctx); + + etm_register_commands(cmd_ctx); return ERROR_OK; }