X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=d900d8ae23981fab090b127b0a69d40920deeaba;hp=a0cde5d4f2d3b71e2ab6c35af06d374761a69731;hb=177bbd8891ae737ea7f8c0791a6236f72cedee40;hpb=23402315ce01071f30d7ec0c5ca7563ce41f1cc6 diff --git a/src/target/arm720t.c b/src/target/arm720t.c index a0cde5d4f2..d900d8ae23 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -225,7 +225,7 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx, static int arm720t_arch_state(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); - struct armv4_5_common_s *armv4_5; + struct arm *armv4_5; static const char *state[] = { @@ -239,8 +239,8 @@ static int arm720t_arch_state(struct target *target) "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), + arm_mode_name(armv4_5->core_mode), + buf_get_u32(armv4_5->cpsr->value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); @@ -307,7 +307,7 @@ static int arm720t_soft_reset_halt(struct target *target) struct arm720t_common *arm720t = target_to_arm720(target); struct reg *dbg_stat = &arm720t->arm7_9_common .eice_cache->reg_list[EICE_DBG_STAT]; - struct armv4_5_common_s *armv4_5 = &arm720t->arm7_9_common + struct arm *armv4_5 = &arm720t->arm7_9_common .armv4_5_common; if ((retval = target_halt(target)) != ERROR_OK) @@ -347,18 +347,19 @@ static int arm720t_soft_reset_halt(struct target *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; + + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; - arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -377,11 +378,24 @@ static int arm720t_init_target(struct command_context *cmd_ctx, struct target *t return arm7tdmi_init_target(cmd_ctx, target); } +/* FIXME remove forward decls */ +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + static int arm720t_init_arch_info(struct target *target, struct arm720t_common *arm720t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; + arm7_9->armv4_5_common.mrc = arm720t_mrc; + arm7_9->armv4_5_common.mcr = arm720t_mcr; + arm7tdmi_init_arch_info(target, arm7_9, tap); arm720t->common_magic = ARM720T_COMMON_MAGIC; @@ -412,11 +426,11 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp) COMMAND_HANDLER(arm720t_handle_cp15_command) { int retval; - struct target *target = get_current_target(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); struct arm720t_common *arm720t = target_to_arm720(target); struct arm_jtag *jtag_info; - retval = arm720t_verify_pointer(cmd_ctx, arm720t); + retval = arm720t_verify_pointer(CMD_CTX, arm720t); if (retval != ERROR_OK) return retval; @@ -424,7 +438,7 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } @@ -439,7 +453,7 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) uint32_t value; if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -448,7 +462,7 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) return retval; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } else if (CMD_ARGC == 2) { @@ -457,10 +471,10 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } } @@ -490,24 +504,29 @@ static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); } -static int arm720t_register_commands(struct command_context *cmd_ctx) -{ - int retval; - struct command *arm720t_cmd; - - - retval = arm7_9_register_commands(cmd_ctx); - - arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", - NULL, COMMAND_ANY, - "arm720t specific commands"); - - register_command(cmd_ctx, arm720t_cmd, "cp15", - arm720t_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register [value]"); +static const struct command_registration arm720t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = arm720t_handle_cp15_command, + .mode = COMMAND_EXEC, + .usage = " [value]", + .help = "display/modify cp15 register", + }, + COMMAND_REGISTRATION_DONE +}; - return ERROR_OK; -} +static const struct command_registration arm720t_command_handlers[] = { + { + .chain = arm7_9_command_handlers, + }, + { + .name = "arm720t", + .mode = COMMAND_ANY, + .help = "arm720t command group", + .chain = arm720t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM720 targets. */ struct target_type arm720t_target = @@ -546,10 +565,8 @@ struct target_type arm720t_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm720t_register_commands, + .commands = arm720t_command_handlers, .target_create = arm720t_target_create, .init_target = arm720t_init_target, .examine = arm7_9_examine, - .mrc = arm720t_mrc, - .mcr = arm720t_mcr, };