X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=d6aa28fb53a80f7fd52dd5c098f1a5c38a10d295;hp=62b70e3b6a657aa5c734d7ec20495d0aad8d439d;hb=86173cdbddde781b19ac630602f2d450a59b32b5;hpb=1aa854684de1827edd3b605fc64a78a498f2358a diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 62b70e3b6a..d6aa28fb53 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -22,11 +22,9 @@ #endif #include "arm720t.h" -#include "jtag.h" -#include "log.h" +#include "time_support.h" +#include "target_type.h" -#include -#include #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ @@ -41,12 +39,12 @@ int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ -int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int arm720t_target_create(struct target_s *target,Jim_Interp *interp); int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm720t_quit(); +int arm720t_quit(void); int arm720t_arch_state(struct target_s *target); -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); +int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); +int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); int arm720t_soft_reset_halt(struct target_s *target); target_type_t arm720t_target = @@ -63,15 +61,15 @@ target_type_t arm720t_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm720t_soft_reset_halt, - .prepare_reset_halt = arm7_9_prepare_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm720t_read_memory, .write_memory = arm720t_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, - + .blank_check_memory = arm7_9_blank_check_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -80,67 +78,69 @@ target_type_t arm720t_target = .remove_watchpoint = arm7_9_remove_watchpoint, .register_commands = arm720t_register_commands, - .target_command = arm720t_target_command, + .target_create = arm720t_target_create, .init_target = arm720t_init_target, + .examine = arm7tdmi_examine, .quit = arm720t_quit }; int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; scan_field_t fields[2]; - u8 out_buf[4]; - u8 instruction_buf = instruction; - + uint8_t out_buf[4]; + uint8_t instruction_buf = instruction; + buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - - jtag_add_end_state(TAP_PD); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - - fields[0].device = jtag_info->chain_pos; + + jtag_set_end_state(TAP_DRPAUSE); + if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + { + return retval; + } + if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) + { + return retval; + } + + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; - fields[0].out_mask = NULL; fields[0].in_value = NULL; - fields[0].in_check_value = NULL; - fields[0].in_check_mask = NULL; - fields[0].in_handler = NULL; - fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = out_buf; - fields[1].out_mask = NULL; fields[1].in_value = NULL; + if (in) { - fields[1].in_handler = arm_jtag_buf_to_u32_flip; - fields[1].in_handler_priv = in; + fields[1].in_value = (uint8_t *)in; + jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_callback(arm7flip32, (uint8_t *)in); } else { - fields[1].in_handler = NULL; - fields[1].in_handler_priv = NULL; + jtag_add_dr_scan(2, fields, jtag_get_end_state()); } - fields[1].in_check_value = NULL; - fields[1].in_check_mask = NULL; - - jtag_add_dr_scan(2, fields, -1, NULL); if (clock) - jtag_add_runtest(0, -1); + jtag_add_runtest(0, jtag_get_end_state()); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } if (in) - DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); + LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); else - DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); #else - DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); #endif return ERROR_OK; @@ -159,7 +159,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) arm720t_scan_cp15(target, 0x0, NULL, 0, 1); /* "EXECUTE" stage (3), CDATA is read */ arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1); - + return ERROR_OK; } @@ -185,9 +185,9 @@ u32 arm720t_get_ttb(target_t *target) arm720t_read_cp15(target, 0xee120f10, &ttb); jtag_execute_queue(); - + ttb &= 0xffffc000; - + return ttb; } @@ -198,10 +198,10 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control &= ~0x1U; - + if (d_u_cache || i_cache) cp15_control &= ~0x4U; @@ -215,13 +215,13 @@ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control |= 0x1U; - + if (d_u_cache || i_cache) cp15_control |= 0x4U; - + arm720t_write_cp15(target, 0xee010f10, cp15_control); } @@ -231,11 +231,11 @@ void arm720t_post_debug_entry(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* examine cp15 control reg */ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); jtag_execute_queue(); - DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; @@ -253,7 +253,7 @@ void arm720t_pre_restore_context(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* restore i/d fault status and address register */ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); @@ -265,35 +265,35 @@ int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar arm7_9_common_t *arm7_9; arm7tdmi_common_t *arm7tdmi; arm720t_common_t *arm720t; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm7tdmi = arm7_9->arch_info; if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC) { return -1; } - + arm720t = arm7tdmi->arch_info; if (arm720t->common_magic != ARM720T_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm7tdmi_p = arm7tdmi; *arm720t_p = arm720t; - + return ERROR_OK; } @@ -303,56 +303,56 @@ int arm720t_arch_state(struct target_s *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - - char *state[] = + + char *state[] = { "disabled", "enabled" }; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - - USER("target halted in %s state due to %s, current mode: %s\n" + + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], - target_debug_reason_strings[target->debug_reason], + Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); - + return ERROR_OK; } -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* disable cache, but leave MMU enabled */ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) arm720t_disable_mmu_caches(target, 0, 1, 0); - + retval = arm7_9_read_memory(target, address, size, count, buffer); - + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) arm720t_enable_mmu_caches(target, 0, 1, 0); - + return retval; } -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) { int retval; - + if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) return retval; @@ -361,75 +361,100 @@ int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou int arm720t_soft_reset_halt(struct target_s *target) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - - if (target->state == TARGET_RUNNING) + + if ((retval = target_halt(target)) != ERROR_OK) { - target->type->halt(target); + return retval; } - - while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { - embeddedice_read_reg(dbg_stat); - jtag_execute_queue(); + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + { + embeddedice_read_reg(dbg_stat); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } + } else + { + break; + } + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } + } + if (timeout) + { + LOG_ERROR("Failed to halt CPU after 1 sec"); + return ERROR_TARGET_TIMEOUT; } - + target->state = TARGET_HALTED; - + /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - + /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - + armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; - + arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); - + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } + return ERROR_OK; } int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm7tdmi_init_target(cmd_ctx, target); - + return ERROR_OK; - } -int arm720t_quit() +int arm720t_quit(void) { - return ERROR_OK; } -int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant) +int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap) { arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; - - arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant); + + arm7tdmi_init_arch_info(target, arm7tdmi, tap); arm7tdmi->arch_info = arm720t; arm720t->common_magic = ARM720T_COMMON_MAGIC; - + arm7_9->post_debug_entry = arm720t_post_debug_entry; arm7_9->pre_restore_context = arm720t_pre_restore_context; - + arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1; arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb; arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory; @@ -438,30 +463,15 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chai arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches; arm720t->armv4_5_mmu.has_tiny_pages = 0; arm720t->armv4_5_mmu.mmu_enabled = 0; - + return ERROR_OK; } -int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int arm720t_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t)); - - if (argc < 4) - { - ERROR("'target arm720t' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; - - DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); - - arm720t_init_arch_info(target, arm720t, chain_pos, variant); + arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); + + arm720t_init_arch_info(target, arm720t, target->tap); return ERROR_OK; } @@ -470,10 +480,10 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm720t_cmd; - - + + retval = arm7tdmi_register_commands(cmd_ctx); - + arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); @@ -486,7 +496,7 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); - + return ERROR_OK; } @@ -505,9 +515,9 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -527,8 +537,12 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); return ERROR_OK; } - jtag_execute_queue(); - + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } + command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); } else if (argc == 2) @@ -547,7 +561,7 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch } int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -560,20 +574,20 @@ int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -586,20 +600,20 @@ int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -612,15 +626,14 @@ int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } -