X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=cc45c9e61f2e1ba5ae146946588a1892ca121b89;hp=31428a2723b68db712c9b2f0e62561f3f8b38e08;hb=938e01d0c3ff4fedf1629cc1c1928af1c90882e9;hpb=82d2633b5f550115e9e7c7d0520babb6680aa38f diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 31428a2723..cc45c9e61f 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -28,7 +28,7 @@ #include #include -#if 1 +#if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif @@ -44,7 +44,7 @@ int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm720t_quit(); -int arm720t_arch_state(struct target_s *target, char *buf, int buf_size); +int arm720t_arch_state(struct target_s *target); int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int arm720t_soft_reset_halt(struct target_s *target); @@ -69,7 +69,9 @@ target_type_t arm720t_target = .read_memory = arm720t_read_memory, .write_memory = arm720t_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, - + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -80,6 +82,7 @@ target_type_t arm720t_target = .register_commands = arm720t_register_commands, .target_command = arm720t_target_command, .init_target = arm720t_init_target, + .examine = arm7tdmi_examine, .quit = arm720t_quit }; @@ -92,12 +95,11 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c u8 out_buf[4]; u8 instruction_buf = instruction; - out = flip_u32(out, 32); - buf_set_u32(out_buf, 0, 32, out); + buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); jtag_add_end_state(TAP_PD); arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); fields[0].device = jtag_info->chain_pos; fields[0].num_bits = 1; @@ -113,14 +115,13 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c fields[1].num_bits = 32; fields[1].out_value = out_buf; fields[1].out_mask = NULL; + fields[1].in_value = NULL; if (in) { - fields[1].in_value = (u8*)in; fields[1].in_handler = arm_jtag_buf_to_u32_flip; fields[1].in_handler_priv = in; } else { - fields[1].in_value = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; } @@ -136,11 +137,11 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c jtag_execute_queue(); if (in) - DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); + LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); else - DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); #else - DEBUG("out: %8.8x, instruction: %i, clock: %i", in, out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); #endif return ERROR_OK; @@ -235,15 +236,15 @@ void arm720t_post_debug_entry(target_t *target) /* examine cp15 control reg */ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); jtag_execute_queue(); - DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; /* save i/d fault status and address register */ - arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr); - arm720t_read_cp15(target, 0xee160f10, &arm720t->far); + arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); + arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg); jtag_execute_queue(); } @@ -255,8 +256,8 @@ void arm720t_pre_restore_context(target_t *target) arm720t_common_t *arm720t = arm7tdmi->arch_info; /* restore i/d fault status and address register */ - arm720t_write_cp15(target, 0xee050f10, arm720t->fsr); - arm720t_write_cp15(target, 0xee060f10, arm720t->far); + arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); + arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); } int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p) @@ -297,7 +298,7 @@ int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar return ERROR_OK; } -int arm720t_arch_state(struct target_s *target, char *buf, int buf_size) +int arm720t_arch_state(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -311,12 +312,11 @@ int arm720t_arch_state(struct target_s *target, char *buf, int buf_size) if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { - ERROR("BUG: called for a non-ARMv4/5 target"); + LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - snprintf(buf, buf_size, - "target halted in %s state due to %s, current mode: %s\n" + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], @@ -366,17 +366,28 @@ int arm720t_soft_reset_halt(struct target_s *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; + int i; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - if (target->state == TARGET_RUNNING) + target_halt(target); + + for (i=0; i<10; i++) { - target->type->halt(target); + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + { + embeddedice_read_reg(dbg_stat); + jtag_execute_queue(); + } else + { + break; + } + /* do not eat all CPU, time out after 1 se*/ + usleep(100*1000); } - - while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0) + if (i==10) { - embeddedice_read_reg(dbg_stat); - jtag_execute_queue(); + LOG_ERROR("Failed to halt CPU after 1 sec"); + return ERROR_TARGET_TIMEOUT; } target->state = TARGET_HALTED; @@ -448,19 +459,20 @@ int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char ** int chain_pos; char *variant = NULL; arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t)); + memset(arm720t, 0, sizeof(*arm720t)); if (argc < 4) { - ERROR("'target arm720t' requires at least one additional argument"); + LOG_ERROR("'target arm720t' requires at least one additional argument"); exit(-1); } chain_pos = strtoul(args[3], NULL, 0); if (argc >= 5) - variant = strdup(args[4]); + variant = args[4]; - DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); + LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); arm720t_init_arch_info(target, arm720t, chain_pos, variant); @@ -475,7 +487,7 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) retval = arm7tdmi_register_commands(cmd_ctx); - arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, NULL); + arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa ");