X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=009336082135dfdea6b72ea9e10e762ff654a9c9;hp=836d347b0b96b88aa74ce3633c48d2709c1e29c4;hb=7f6bab0c4c36d7a64f933904e5add9bc6b36d78c;hpb=0442bda216ef89a212f1dc58591db6edfd6b9f08 diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 836d347b0b..0093360821 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -25,101 +25,48 @@ #endif #include "arm720t.h" -#include "time_support.h" +#include #include "target_type.h" +#include "register.h" +#include "arm_opcodes.h" +/* + * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see + * ARM DDI 0229C especially Chapter 9 about debug support. + */ + #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm720t_register_commands(struct command_context_s *cmd_ctx); - -int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm720t_target_create(struct target_s *target,Jim_Interp *interp); -int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm720t_arch_state(struct target_s *target); -int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm720t_soft_reset_halt(struct target_s *target); - -static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value); -static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value); - -target_type_t arm720t_target = -{ - .name = "arm720t", - - .poll = arm7_9_poll, - .arch_state = arm720t_arch_state, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm720t_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm720t_read_memory, - .write_memory = arm720t_write_memory, - .read_phys_memory = arm720t_read_phys_memory, - .write_phys_memory = arm720t_write_phys_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm720t_register_commands, - .target_create = arm720t_target_create, - .init_target = arm720t_init_target, - .examine = arm7tdmi_examine, - .mrc = arm720t_mrc, - .mcr = arm720t_mcr, - -}; - -int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock) +static int arm720t_scan_cp15(struct target *target, + uint32_t out, uint32_t *in, int instruction, int clock) { - int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[2]; + int retval; + struct arm720t_common *arm720t = target_to_arm720(target); + struct arm_jtag *jtag_info; + struct scan_field fields[2]; uint8_t out_buf[4]; uint8_t instruction_buf = instruction; + jtag_info = &arm720t->arm7_9_common.jtag_info; + buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK) { return retval; } - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) + if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK) { return retval; } - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = out_buf; fields[1].in_value = NULL; @@ -127,15 +74,15 @@ int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruct if (in) { fields[1].in_value = (uint8_t *)in; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else { - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); } if (clock) - jtag_add_runtest(0, jtag_get_end_state()); + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -154,7 +101,7 @@ int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruct return ERROR_OK; } -int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value) +static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -171,7 +118,7 @@ int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value) return ERROR_OK; } -int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value) +static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -187,7 +134,7 @@ int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value) return ERROR_OK; } -uint32_t arm720t_get_ttb(target_t *target) +static uint32_t arm720t_get_ttb(struct target *target) { uint32_t ttb = 0x0; @@ -199,7 +146,8 @@ uint32_t arm720t_get_ttb(target_t *target) return ttb; } -void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void arm720t_disable_mmu_caches(struct target *target, + int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -216,7 +164,8 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ arm720t_write_cp15(target, 0xee010f10, cp15_control); } -void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static void arm720t_enable_mmu_caches(struct target *target, + int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -233,12 +182,9 @@ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c arm720t_write_cp15(target, 0xee010f10, cp15_control); } -void arm720t_post_debug_entry(target_t *target) +static void arm720t_post_debug_entry(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); /* examine cp15 control reg */ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); @@ -255,95 +201,79 @@ void arm720t_post_debug_entry(target_t *target) jtag_execute_queue(); } -void arm720t_pre_restore_context(target_t *target) +static void arm720t_pre_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); /* restore i/d fault status and address register */ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); } -int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p) +static int arm720t_verify_pointer(struct command_context *cmd_ctx, + struct arm720t_common *arm720t) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; + if (arm720t->common_magic != ARM720T_COMMON_MAGIC) { + command_print(cmd_ctx, "target is not an ARM720"); + return ERROR_TARGET_INVALID; } + return ERROR_OK; +} - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } +static int arm720t_arch_state(struct target *target) +{ + struct arm720t_common *arm720t = target_to_arm720(target); + struct arm *armv4_5; - arm7tdmi = arm7_9->arch_info; - if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC) + static const char *state[] = { - return -1; - } + "disabled", "enabled" + }; - arm720t = arm7tdmi->arch_info; - if (arm720t->common_magic != ARM720T_COMMON_MAGIC) - { - return -1; - } + armv4_5 = &arm720t->arm7_9_common.armv4_5_common; - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm7tdmi_p = arm7tdmi; - *arm720t_p = arm720t; + arm_arch_state(target); + LOG_USER("MMU: %s, Cache: %s", + state[arm720t->armv4_5_mmu.mmu_enabled], + state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); return ERROR_OK; } -int arm720t_arch_state(struct target_s *target) +static int arm720_mmu(struct target *target, int *enabled) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + if (target->state != TARGET_HALTED) { + LOG_ERROR("%s: target not halted", __func__); + return ERROR_TARGET_INVALID; + } - char *state[] = - { - "disabled", "enabled" - }; + *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled; + return ERROR_OK; +} - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) +static int arm720_virt2phys(struct target *target, + uint32_t virtual, uint32_t *physical) +{ + int type; + uint32_t cb; + int domain; + uint32_t ap; + struct arm720t_common *arm720t = target_to_arm720(target); + + uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); + if (type == -1) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + return ret; } - - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), - state[arm720t->armv4_5_mmu.mmu_enabled], - state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); - + *physical = ret; return ERROR_OK; } -int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm720t_read_memory(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); /* disable cache, but leave MMU enabled */ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) @@ -357,46 +287,30 @@ int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size return retval; } -int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm720t_read_phys_memory(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - int retval; - - if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) - return retval; - - return retval; -} - - -int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); } -int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm720t_write_phys_memory(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); } - -int arm720t_soft_reset_halt(struct target_s *target) +static int arm720t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm720t_common *arm720t = target_to_arm720(target); + struct reg *dbg_stat = &arm720t->arm7_9_common + .eice_cache->reg_list[EICE_DBG_STAT]; + struct arm *armv4_5 = &arm720t->arm7_9_common + .armv4_5_common; if ((retval = target_halt(target)) != ERROR_OK) { @@ -435,17 +349,18 @@ int arm720t_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; - /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; + /* start fetching from 0x0 */ + buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); + armv4_5->pc->dirty = 1; + armv4_5->pc->valid = 1; arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; @@ -460,22 +375,31 @@ int arm720t_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target) { - arm7tdmi_init_target(cmd_ctx, target); - - return ERROR_OK; + return arm7tdmi_init_target(cmd_ctx, target); } - -int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap) +/* FIXME remove forward decls */ +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + +static int arm720t_init_arch_info(struct target *target, + struct arm720t_common *arm720t, struct jtag_tap *tap) { - arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; - arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; + + arm7_9->armv4_5_common.mrc = arm720t_mrc; + arm7_9->armv4_5_common.mcr = arm720t_mcr; - arm7tdmi_init_arch_info(target, arm7tdmi, tap); + arm7tdmi_init_arch_info(target, arm7_9, tap); - arm7tdmi->arch_info = arm720t; arm720t->common_magic = ARM720T_COMMON_MAGIC; arm7_9->post_debug_entry = arm720t_post_debug_entry; @@ -493,66 +417,45 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap return ERROR_OK; } -int arm720t_target_create(struct target_s *target, Jim_Interp *interp) +static int arm720t_target_create(struct target *target, Jim_Interp *interp) { - arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); + struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - arm720t_init_arch_info(target, arm720t, target->tap); - - return ERROR_OK; + arm720t->arm7_9_common.armv4_5_common.is_armv4 = true; + return arm720t_init_arch_info(target, arm720t, target->tap); } -int arm720t_register_commands(struct command_context_s *cmd_ctx) +COMMAND_HANDLER(arm720t_handle_cp15_command) { int retval; - command_t *arm720t_cmd; - - - retval = arm7tdmi_register_commands(cmd_ctx); + struct target *target = get_current_target(CMD_CTX); + struct arm720t_common *arm720t = target_to_arm720(target); + struct arm_jtag *jtag_info; - arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); - - register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - - return ERROR_OK; -} - -int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) -{ - int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } + retval = arm720t_verify_pointer(CMD_CTX, arm720t); + if (retval != ERROR_OK) + return retval; - jtag_info = &arm7_9->jtag_info; + jtag_info = &arm720t->arm7_9_common.jtag_info; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + if (CMD_ARGC >= 1) { uint32_t opcode; - COMMAND_PARSE_NUMBER(u32, args[0], opcode); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -561,27 +464,29 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch return retval; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[1], value); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } } return ERROR_OK; } - -static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { if (cpnum!=15) { @@ -589,11 +494,17 @@ static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return ERROR_FAIL; } - return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); + /* read "to" r0 */ + return arm720t_read_cp15(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + value); } -static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { if (cpnum!=15) { @@ -601,7 +512,78 @@ static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, return ERROR_FAIL; } - return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value); + /* write "from" r0 */ + return arm720t_write_cp15(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + value); } +static const struct command_registration arm720t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = arm720t_handle_cp15_command, + .mode = COMMAND_EXEC, + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value]", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm720t_command_handlers[] = { + { + .chain = arm7_9_command_handlers, + }, + { + .name = "arm720t", + .mode = COMMAND_ANY, + .help = "arm720t command group", + .chain = arm720t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +/** Holds methods for ARM720 targets. */ +struct target_type arm720t_target = +{ + .name = "arm720t", + + .poll = arm7_9_poll, + .arch_state = arm720t_arch_state, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm720t_soft_reset_halt, + + .get_gdb_reg_list = arm_get_gdb_reg_list, + + .read_memory = arm720t_read_memory, + .write_memory = arm7_9_write_memory, + .read_phys_memory = arm720t_read_phys_memory, + .write_phys_memory = arm720t_write_phys_memory, + .mmu = arm720_mmu, + .virt2phys = arm720_virt2phys, + + .bulk_write_memory = arm7_9_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .commands = arm720t_command_handlers, + .target_create = arm720t_target_create, + .init_target = arm720t_init_target, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, +};