X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=554d6e2b99f7acdb3166a62be308a8fc1851ecc9;hp=7360717625c8c85c780161e85e7628f0612afb0a;hb=cfd79e96a6436cea427245a2c2f18fd52001898b;hpb=4866c8ed25ebc915db51824046589547f1f8585d diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 7360717625..554d6e2b99 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -1,7 +1,8 @@ /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * * * - * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -23,73 +24,105 @@ #include "config.h" #endif -#include "arm11.h" -#include "jtag.h" -#include "log.h" +#include "arm_jtag.h" +#include "arm11_dbgtap.h" -#include -#include +#include #if 0 -#define JTAG_DEBUG(expr ...) DEBUG(expr) +#define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0) #else -#define JTAG_DEBUG(expr ...) do {} while(0) +#define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0) #endif -tap_state_t arm11_move_pi_to_si_via_ci[] = +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ +static const tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; -int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +static int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, + tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) - jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(num_fields, fields, state); return ERROR_OK; } -tap_state_t arm11_move_pd_to_sd_via_cd[] = +static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) - jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(num_fields, fields, state); return ERROR_OK; } -/** Code de-clutter: Construct scan_field_t to write out a value +/** Code de-clutter: Construct struct scan_field to write out a value * * \param arm11 Target state variable. * \param num_bits Length of the data field * \param out_data pointer to the data that will be sent out - * (data is read when it is added to the JTAG queue) + * (data is read when it is added to the JTAG queue) * \param in_data pointer to the memory that will receive data that was clocked in - * (data is written when the JTAG queue is executed) + * (data is written when the JTAG queue is executed) * \param field target data structure that will be initialized */ -void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field) +void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) { - field->tap = arm11->jtag_info.tap; + field->tap = arm11->arm.target->tap; field->num_bits = num_bits; - field->out_mask = NULL; - field->in_check_mask = NULL; - field->in_check_value = NULL; - field->in_handler = NULL; - field->in_handler_priv = NULL; - field->out_value = out_data; field->in_value = in_data; } +static const char *arm11_ir_to_string(uint8_t ir) +{ + const char *s = "unknown"; + + switch (ir) { + case ARM11_EXTEST: + s = "EXTEST"; + break; + case ARM11_SCAN_N: + s = "SCAN_N"; + break; + case ARM11_RESTART: + s = "RESTART"; + break; + case ARM11_HALT: + s = "HALT"; + break; + case ARM11_INTEST: + s = "INTEST"; + break; + case ARM11_ITRSEL: + s = "ITRSEL"; + break; + case ARM11_IDCODE: + s = "IDCODE"; + break; + case ARM11_BYPASS: + s = "BYPASS"; + break; + } + return s; +} /** Write JTAG instruction register * @@ -99,10 +132,9 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) +void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) { - jtag_tap_t *tap; - tap = arm11->jtag_info.tap; + struct jtag_tap *tap = arm11->arm.target->tap; if (buf_get_u32(tap->cur_instr, 0, 5) == instr) { @@ -110,9 +142,9 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) return; } - JTAG_DEBUG("IR <= 0x%02x", instr); + JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr); - scan_field_t field; + struct scan_field field; arm11_setup_field(arm11, 5, &instr, NULL, &field); @@ -120,23 +152,23 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) } /** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to scan_field_t::in_handler in + * Used as parameter to struct scan_field::in_handler in * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(uint8_t *in_value) { - /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ - u8 v = *in_value & 0x1F; + /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ + uint8_t v = *in_value & 0x1F; if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + jtag_set_error(ERROR_FAIL); } - JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; + if (v != 0x10) + JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); } /** Select and write to Scan Chain Register (SCREG) @@ -151,6 +183,9 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default * value (Pause-DR). * + * Changes the current scan chain if needed, transitions to the specified + * TAP state, and leaves the IR undefined. + * * The chain takes effect when Update-DR is passed (usually when subsequently * the INTEXT/EXTEST instructions are written). * @@ -163,86 +198,106 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) +int arm11_add_debug_SCAN_N(struct arm11_common *arm11, + uint8_t chain, tap_state_t state) { - JTAG_DEBUG("SCREG <= 0x%02x", chain); + /* Don't needlessly switch the scan chain. + * NOTE: the ITRSEL instruction fakes SCREG changing; + * but leaves its actual value unchanged. + */ + if (arm11->jtag_info.cur_scan_chain == chain) { + JTAG_DEBUG("SCREG <= %d SKIPPED", chain); + return jtag_add_statemove((state == ARM11_TAP_DEFAULT) + ? TAP_DRPAUSE : state); + } + JTAG_DEBUG("SCREG <= %d", chain); arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); - scan_field_t field; - - arm11_setup_field(arm11, 5, &chain, NULL, &field); + struct scan_field field; - field.in_handler = arm11_in_handler_SCAN_N; + uint8_t tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + + jtag_execute_queue_noclear(); + + arm11_in_handler_SCAN_N(tmp); + + arm11->jtag_info.cur_scan_chain = chain; + + return jtag_execute_queue(); } -/** Write an instruction into the ITR register +/** + * Queue a DR scan of the ITR register. Caller must have selected + * scan chain 4 (ITR), possibly using ITRSEL. * * \param arm11 Target state variable. * \param inst An ARM11 processor instruction/opcode. - * \param flag Optional parameter to retrieve the InstCompl flag - * (this will be written when the JTAG chain is executed). - * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default - * value (Run-Test/Idle). + * \param flag Optional parameter to retrieve the Ready flag; + * this address will be written when the JTAG chain is scanned. + * \param state The TAP state to enter after the DR scan. * - * \remarks By default this ends with Run-Test/Idle state - * and causes the instruction to be executed. If - * a subsequent write to DTR is needed before - * executing the instruction then TAP_DRPAUSE should be - * passed to \p state. + * Going through the TAP_DRUPDATE state writes ITR only if Ready was + * previously set. Only the Ready flag is readable by the scan. * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * An instruction loaded into ITR is executed when going through the + * TAP_IDLE state only if Ready was previously set and the debug state + * is properly set up. Depending on the instruction, you may also need + * to ensure that the rDTR is ready before that Run-Test/Idle state. */ -void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state) +static void arm11_add_debug_INST(struct arm11_common * arm11, + uint32_t inst, uint8_t * flag, tap_state_t state) { - JTAG_DEBUG("INST <= 0x%08x", inst); + JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst); - scan_field_t itr[2]; + struct scan_field itr[2]; arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); + arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state); } -/** Read the Debug Status and Control Register (DSCR) - * - * same as CP14 c1 +/** + * Read and save the Debug Status and Control Register (DSCR). * * \param arm11 Target state variable. - * \return DSCR content + * \return Error status; arm11->dscr is updated on success. * - * \remarks This is a stand-alone function that executes the JTAG command queue. + * \remarks This is a stand-alone function that executes the JTAG + * command queue. It does not require the ARM11 debug TAP to be + * in any particular state. */ -int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) +int arm11_read_DSCR(struct arm11_common *arm11) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - u32 dscr; - scan_field_t chain1_field; + uint32_t dscr; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - int retval; - if ((retval=jtag_execute_queue())!=ERROR_OK) - { - return retval; - } - - if (arm11->last_dscr != dscr) - JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); + CHECK_RETVAL(jtag_execute_queue()); - arm11->last_dscr = dscr; + if (arm11->dscr != dscr) + JTAG_DEBUG("DSCR = %08x (OLD %08x)", + (unsigned) dscr, + (unsigned) arm11->dscr); - *value=dscr; + arm11->dscr = dscr; - return retval; + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) @@ -254,68 +309,31 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) +int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain1_field; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - jtag_execute_queue(); - - JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); - - arm11->last_dscr = dscr; -} - - + CHECK_RETVAL(jtag_execute_queue()); -/** Get the debug reason from Debug Status and Control Register (DSCR) - * - * \param dscr DSCR value to analyze - * \return Debug reason - * - */ -enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) -{ - switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK) - { - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT: - LOG_INFO("Debug entry: JTAG HALT"); - return DBG_REASON_DBGRQ; - - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT: - LOG_INFO("Debug entry: breakpoint"); - return DBG_REASON_BREAKPOINT; - - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT: - LOG_INFO("Debug entry: watchpoint"); - return DBG_REASON_WATCHPOINT; - - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION: - LOG_INFO("Debug entry: BKPT instruction"); - return DBG_REASON_BREAKPOINT; - - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ: - LOG_INFO("Debug entry: EDBGRQ signal"); - return DBG_REASON_DBGRQ; - - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH: - LOG_INFO("Debug entry: VCR vector catch"); - return DBG_REASON_BREAKPOINT; - - default: - LOG_INFO("Debug entry: unknown"); - return DBG_REASON_DBGRQ; - } -}; + JTAG_DEBUG("DSCR <= %08x (OLD %08x)", + (unsigned) dscr, + (unsigned) arm11->dscr); + arm11->dscr = dscr; + return ERROR_OK; +} /** Prepare the stage for ITR/DTR operations * from the arm11_run_instr... group of functions. @@ -331,9 +349,9 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_prepare(arm11_common_t * arm11) +int arm11_run_instr_data_prepare(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); } /** Cleanup after ITR/DTR operations @@ -350,13 +368,18 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_finish(arm11_common_t * arm11) +int arm11_run_instr_data_finish(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); } -/** Execute one or multiple instructions via ITR + +/** + * Execute one or more instructions via ITR. + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block * @@ -365,7 +388,9 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) * \param count Number of opcodes to execute * */ -void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) +static +int arm11_run_instr_no_data(struct arm11_common * arm11, + uint32_t * opcode, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -373,18 +398,38 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) { arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); + int i = 0; while (1) { - u8 flag; + uint8_t flag; arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); if (flag) break; + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -395,15 +440,19 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) * \param opcode ARM opcode * */ -void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) +int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) { - arm11_run_instr_no_data(arm11, &opcode, 1); + return arm11_run_instr_no_data(arm11, &opcode, 1); } /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must read data from DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -414,7 +463,7 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -422,11 +471,11 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); @@ -434,14 +483,33 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data while (count--) { + int i = 0; do { Data = *data; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); @@ -450,16 +518,38 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + int i = 0; do { Data = 0; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + CHECK_RETVAL(jtag_execute_queue()); + + JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", + (unsigned) Data, Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); + + return ERROR_OK; } /** JTAG path for arm11_run_instr_data_to_core_noack @@ -472,8 +562,14 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * + * FIX!!! should we use multiple TAP_IDLE here or not??? + * + * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html + * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = +static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -483,6 +579,10 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * No Ready check during transmission. * * The executed instruction \em must read data from DTR. @@ -495,7 +595,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -503,14 +603,24 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - u8 Readies[count + 1]; - u8 * ReadyPos = Readies; + uint8_t *Readies; + unsigned readiesNum = count + 1; + unsigned bytes = sizeof(*Readies)*readiesNum; + + Readies = (uint8_t *) malloc(bytes); + if (Readies == NULL) + { + LOG_ERROR("Out of memory allocating %u bytes", bytes); + return ERROR_FAIL; + } + + uint8_t * ReadyPos = Readies; while (count--) { @@ -519,13 +629,13 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 if (count) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), + jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE)); + jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); } else { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE); + jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); } } @@ -534,23 +644,30 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 chain5_fields[0].out_value = 0; chain5_fields[1].in_value = ReadyPos++; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); - size_t error_count = 0; - - {size_t i; - for (i = 0; i < asizeof(Readies); i++) + int retval = jtag_execute_queue(); + if (retval == ERROR_OK) { - if (Readies[i] != 1) + unsigned error_count = 0; + + for (size_t i = 0; i < readiesNum; i++) { - error_count++; + if (Readies[i] != 1) + { + error_count++; + } } - }} - if (error_count) - LOG_ERROR("Transfer errors " ZU, error_count); + if (error_count > 0 ) + LOG_ERROR("%u words out of %u not transferred", + error_count, readiesNum); + + } + + free(Readies); + + return retval; } @@ -565,15 +682,19 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * \param data Data word to be passed to the core via DTR * */ -void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { - arm11_run_instr_data_to_core(arm11, opcode, &data, 1); + return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } /** Execute one instruction via ITR repeatedly while * reading data from the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must write data to DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -584,7 +705,7 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -592,11 +713,11 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); @@ -604,17 +725,39 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da while (count--) { + int i = 0; do { - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); + + CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", + (unsigned) Data, Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); *data++ = Data; } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -629,12 +772,17 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed. * */ -void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data) +int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data) { - arm11_run_instr_no_data1(arm11, opcode); + int retval; + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */ arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1); + + return ERROR_OK; } /** Load data into core via DTR then move it to r0 then @@ -649,44 +797,54 @@ void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u * \param data Data word that will be written to r0 before \p opcode is executed * */ -void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { + int retval; /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + if (retval != ERROR_OK) + return retval; - arm11_run_instr_no_data1(arm11, opcode); + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; } /** Apply reads and writes to scan chain 7 * - * \see arm11_sc7_action_t + * \see struct arm11_sc7_action * * \param arm11 Target state variable. * \param actions A list of read and/or write instructions * \param count Number of instructions in the list. * */ -void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) +int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count) { - arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + int retval; + + retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain7_fields[3]; + struct scan_field chain7_fields[3]; - u8 nRW; - u32 DataOut; - u8 AddressOut; - u8 Ready; - u32 DataIn; - u8 AddressIn; + uint8_t nRW; + uint32_t DataOut; + uint8_t AddressOut; + uint8_t Ready; + uint32_t DataIn; + uint8_t AddressIn; arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - {size_t i; - for (i = 0; i < count + 1; i++) + for (size_t i = 0; i < count + 1; i++) { if (i < count) { @@ -696,22 +854,31 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t } else { - nRW = 0; + nRW = 1; DataOut = 0; AddressOut = 0; } do { - JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); + JTAG_DEBUG("SC7 <= c%-3d Data %08x %s", + (unsigned) AddressOut, + (unsigned) DataOut, + nRW ? "write" : "read"); + + arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), + chain7_fields, TAP_DRPAUSE); - arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); - JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); + if (!Ready) + JTAG_DEBUG("SC7 => !ready"); } while (!Ready); /* 'nRW' is 'Ready' on read out */ + if (!nRW) + JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn); + if (i > 0) { if (actions[i - 1].address != AddressIn) @@ -731,13 +898,8 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t } } } - }} - - {size_t i; - for (i = 0; i < count; i++) - { - JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); - }} + } + return ERROR_OK; } /** Clear VCR and all breakpoints and watchpoints via scan chain 7 @@ -745,31 +907,26 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t * \param arm11 Target state variable. * */ -void arm11_sc7_clear_vbw(arm11_common_t * arm11) +void arm11_sc7_clear_vbw(struct arm11_common * arm11) { - arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; - arm11_sc7_action_t * pos = clear_bw; + size_t clear_bw_size = arm11->brp + 1; + struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size); + struct arm11_sc7_action * pos = clear_bw; - {size_t i; - for (i = 0; i < asizeof(clear_bw); i++) + for (size_t i = 0; i < clear_bw_size; i++) { clear_bw[i].write = true; clear_bw[i].value = 0; - }} - - {size_t i; - for (i = 0; i < arm11->brp; i++) - (pos++)->address = ARM11_SC7_BCR0 + i; } - {size_t i; - for (i = 0; i < arm11->wrp; i++) - (pos++)->address = ARM11_SC7_WCR0 + i; - } + for (size_t i = 0; i < arm11->brp; i++) + (pos++)->address = ARM11_SC7_BCR0 + i; (pos++)->address = ARM11_SC7_VCR; - arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw)); + arm11_sc7_run(arm11, clear_bw, clear_bw_size); + + free (clear_bw); } /** Write VCR register @@ -777,15 +934,14 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) * \param arm11 Target state variable. * \param value Value to be written */ -void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) +void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) { - arm11_sc7_action_t set_vcr; + struct arm11_sc7_action set_vcr; set_vcr.write = true; set_vcr.address = ARM11_SC7_VCR; set_vcr.value = value; - arm11_sc7_run(arm11, &set_vcr, 1); } @@ -798,17 +954,194 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) * \param result Pointer where to store result * */ -void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) +int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result) { - arm11_run_instr_data_prepare(arm11); + int retval; + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1); + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); + + return arm11_run_instr_data_finish(arm11); +} + + +/************************************************************************/ + +/* + * ARM11 provider for the OpenOCD implementation of the standard + * architectural ARM v6/v7 "Debug Programmer's Model" (DPM). + */ + +static inline struct arm11_common *dpm_to_arm11(struct arm_dpm *dpm) +{ + return container_of(dpm, struct arm11_common, dpm); +} + +static int arm11_dpm_prepare(struct arm_dpm *dpm) +{ + struct arm11_common *arm11 = dpm_to_arm11(dpm); + + arm11 = container_of(dpm->arm, struct arm11_common, arm); + + return arm11_run_instr_data_prepare(dpm_to_arm11(dpm)); +} + +static int arm11_dpm_finish(struct arm_dpm *dpm) +{ + return arm11_run_instr_data_finish(dpm_to_arm11(dpm)); +} + +static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm, + uint32_t opcode, uint32_t data) +{ + return arm11_run_instr_data_to_core(dpm_to_arm11(dpm), + opcode, &data, 1); +} + +static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm, + uint32_t opcode, uint32_t data) +{ + return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm), + opcode, data); +} - arm11_run_instr_data_finish(arm11); +static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm, + uint32_t opcode, uint32_t *data) +{ + return arm11_run_instr_data_from_core(dpm_to_arm11(dpm), + opcode, data, 1); } +static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm, + uint32_t opcode, uint32_t *data) +{ + return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm), + opcode, data); +} +/* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint + * and watchpoint operations instead of running them right away. Since we + * pre-allocated our vector, we don't need to worry about space. + */ +static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index, + uint32_t addr, uint32_t control) +{ + struct arm11_common *arm11 = dpm_to_arm11(dpm); + struct arm11_sc7_action *action; + + action = arm11->bpwp_actions + arm11->bpwp_n; + + /* Invariant: this bp/wp is disabled. + * It also happens that the core is halted here, but for + * DPM-based cores we don't actually care about that. + */ + + action[0].write = action[1].write = true; + + action[0].value = addr; + action[1].value = control; + + switch (index) { + case 0 ... 15: + action[0].address = ARM11_SC7_BVR0 + index; + action[1].address = ARM11_SC7_BCR0 + index; + break; + case 16 ... 32: + index -= 16; + action[0].address = ARM11_SC7_WVR0 + index; + action[1].address = ARM11_SC7_WCR0 + index; + break; + default: + return ERROR_FAIL; + } + + arm11->bpwp_n += 2; + + return ERROR_OK; +} + +static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index) +{ + struct arm11_common *arm11 = dpm_to_arm11(dpm); + struct arm11_sc7_action *action; + + action = arm11->bpwp_actions + arm11->bpwp_n; + + action[0].write = true; + action[0].value = 0; + + switch (index) { + case 0 ... 15: + action[0].address = ARM11_SC7_BCR0 + index; + break; + case 16 ... 32: + index -= 16; + action[0].address = ARM11_SC7_WCR0 + index; + break; + default: + return ERROR_FAIL; + } + + arm11->bpwp_n += 1; + + return ERROR_OK; +} + +/** Flush any pending breakpoint and watchpoint updates. */ +int arm11_bpwp_flush(struct arm11_common *arm11) +{ + int retval; + + if (!arm11->bpwp_n) + return ERROR_OK; + + retval = arm11_sc7_run(arm11, arm11->bpwp_actions, arm11->bpwp_n); + arm11->bpwp_n = 0; + + return retval; +} + +/** Set up high-level debug module utilities */ +int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr) +{ + struct arm_dpm *dpm = &arm11->dpm; + int retval; + + dpm->arm = &arm11->arm; + + dpm->didr = didr; + + dpm->prepare = arm11_dpm_prepare; + dpm->finish = arm11_dpm_finish; + + dpm->instr_write_data_dcc = arm11_dpm_instr_write_data_dcc; + dpm->instr_write_data_r0 = arm11_dpm_instr_write_data_r0; + + dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc; + dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0; + + dpm->bpwp_enable = arm11_bpwp_enable; + dpm->bpwp_disable = arm11_bpwp_disable; + + retval = arm_dpm_setup(dpm); + if (retval != ERROR_OK) + return retval; + + /* alloc enough to enable all breakpoints and watchpoints at once */ + arm11->bpwp_actions = calloc(2 * (dpm->nbp + dpm->nwp), + sizeof *arm11->bpwp_actions); + if (!arm11->bpwp_actions) + return ERROR_FAIL; + + retval = arm_dpm_initialize(dpm); + if (retval != ERROR_OK) + return retval; + + return arm11_bpwp_flush(arm11); +}