X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=b397709a82c287afd45a0ab234df0e648237edc0;hp=aa36b2934d74e1735ab13681cc5778a0042a8595;hb=74d09617b927ed7011098d5a65087dee1ef1e87a;hpb=ed8fd94d7ca0fc0682de4020501afae89f31ccc3 diff --git a/src/target/arm11.h b/src/target/arm11.h index aa36b2934d..b397709a82 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -33,8 +33,9 @@ type * variable = calloc(1, sizeof(type) * items) /* For MinGW use 'I' prefix to print size_t (instead of 'z') */ +/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */ -#ifndef __MSVCRT__ +#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO)) #define ZU "%zu" #else #define ZU "%Iu" @@ -63,11 +64,11 @@ do { \ } while (0) -typedef struct arm11_register_history_s +struct arm11_register_history { uint32_t value; uint8_t valid; -}arm11_register_history_t; +}; enum arm11_debug_version { @@ -77,7 +78,7 @@ enum arm11_debug_version ARM11_DEBUG_V7_CP14 = 0x04, }; -typedef struct arm11_common_s +struct arm11_common { target_t * target; /**< Reference back to the owner */ @@ -98,10 +99,6 @@ typedef struct arm11_common_s uint32_t last_dscr; /**< Last retrieved DSCR value; Use only for debug message generation */ - bool trst_active; - bool halt_requested; /**< Keep track if arm11_halt() calls occured - during reset. Otherwise do it ASAP. */ - bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ /** \name Shadow registers to save processor state */ @@ -112,15 +109,15 @@ typedef struct arm11_common_s /*@}*/ - arm11_register_history_t + struct arm11_register_history reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */ // GA - reg_cache_t *core_cache; -} arm11_common_t; + struct reg_cache *core_cache; +}; /** @@ -179,114 +176,17 @@ enum arm11_sc7 ARM11_SC7_WCR0 = 112, }; -typedef struct arm11_reg_state_s +struct arm11_reg_state { uint32_t def_index; target_t * target; -} arm11_reg_state_t; - -/* poll current target status */ -int arm11_poll(struct target_s *target); -/* architecture specific status reply */ -int arm11_arch_state(struct target_s *target); - -/* target request support */ -int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer); - -/* target execution control */ -int arm11_halt(struct target_s *target); -int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int arm11_examine(struct target_s *target); - -/* target reset control */ -int arm11_assert_reset(struct target_s *target); -int arm11_deassert_reset(struct target_s *target); -int arm11_soft_reset_halt(struct target_s *target); - -/* target register access for gdb */ -int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size); - -/* target memory access -* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) -* count: number of items of -*/ -int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - -/* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer); - -int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum); - -/* target break-/watchpoint control -* rw: 0 = write, 1 = read, 2 = access -*/ -int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); - -/* target algorithm support */ -int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info); +}; int arm11_register_commands(struct command_context_s *cmd_ctx); -int arm11_target_create(struct target_s *target, Jim_Interp *interp); -int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm11_quit(void); - -/* helpers */ -int arm11_build_reg_cache(target_t *target); -int arm11_set_reg(reg_t *reg, uint8_t *buf); -int arm11_get_reg(reg_t *reg); - -void arm11_record_register_history(arm11_common_t * arm11); -void arm11_dump_reg_changes(arm11_common_t * arm11); - -/* internals */ - -void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field); -void arm11_add_IR (arm11_common_t * arm11, uint8_t instr, tap_state_t state); -void arm11_add_debug_SCAN_N (arm11_common_t * arm11, uint8_t chain, tap_state_t state); -void arm11_add_debug_INST (arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state); -int arm11_read_DSCR (arm11_common_t * arm11, uint32_t *dscr); -int arm11_write_DSCR (arm11_common_t * arm11, uint32_t dscr); - -enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr); - -void arm11_run_instr_data_prepare (arm11_common_t * arm11); -void arm11_run_instr_data_finish (arm11_common_t * arm11); -int arm11_run_instr_no_data (arm11_common_t * arm11, uint32_t * opcode, size_t count); -int arm11_run_instr_no_data1 (arm11_common_t * arm11, uint32_t opcode); -int arm11_run_instr_data_to_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count); -int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count); -int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, uint32_t opcode, uint32_t data); -int arm11_run_instr_data_from_core (arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count); -int arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t * data); -void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, uint32_t opcode, uint32_t data); - -int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state); -int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state); - -/** Used to make a list of read/write commands for scan chain 7 - * - * Use with arm11_sc7_run() - */ -typedef struct arm11_sc7_action_s -{ - bool write; /**< Access mode: true for write, false for read. */ - uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */ - uint32_t value; /**< If write then set this to value to be written. - In read mode this receives the read value when the - function returns. */ -} arm11_sc7_action_t; -int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count); +int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value); +int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value); -/* Mid-level helper functions */ -void arm11_sc7_clear_vbw(arm11_common_t * arm11); -void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value); -int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result); #endif /* ARM11_H */