X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=9edadee1d911681f4f7b80c5305e0223b32c321f;hp=809c23fbf72998e5c74085800042d0ad5f5be943;hb=b48d1f66378fac886d5bc32d7302da48c89d8a75;hpb=dc1685ca25567fe75c8d50c825fb0303fbb66fac diff --git a/src/target/arm11.h b/src/target/arm11.h index 809c23fbf7..9edadee1d9 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -23,49 +23,22 @@ #ifndef ARM11_H #define ARM11_H -#include "armv4_5.h" - -#define NEW(type, variable, items) \ - type * variable = calloc(1, sizeof(type) * items) - -/* For MinGW use 'I' prefix to print size_t (instead of 'z') */ -/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */ - -#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO)) -#define ZU "%zu" -#else -#define ZU "%Iu" -#endif - -#define ARM11_REGCACHE_MODEREGS 0 -#define ARM11_REGCACHE_FREGS 0 - -#define ARM11_REGCACHE_COUNT (20 + \ - 23 * ARM11_REGCACHE_MODEREGS + \ - 9 * ARM11_REGCACHE_FREGS) +#include "arm.h" +#include "arm_dpm.h" #define ARM11_TAP_DEFAULT TAP_INVALID - -#define CHECK_RETVAL(action) \ -do { \ - int __retval = (action); \ - \ - if (__retval != ERROR_OK) \ - { \ - LOG_DEBUG("error while calling \"" # action "\""); \ - return __retval; \ - } \ - \ -} while (0) - - -struct arm11_register_history -{ - uint32_t value; - uint8_t valid; -}; - +#define CHECK_RETVAL(action) \ + do { \ + int __retval = (action); \ + if (__retval != ERROR_OK) { \ + LOG_DEBUG("error while calling \"%s\"", \ + # action ); \ + return __retval; \ + } \ + } while (0) + +/* bits from ARMv7 DIDR */ enum arm11_debug_version { ARM11_DEBUG_V6 = 0x01, @@ -77,43 +50,36 @@ enum arm11_debug_version struct arm11_common { struct arm arm; - struct target * target; /**< Reference back to the owner */ - - /** \name Processor type detection */ - /*@{*/ - uint32_t device_id; /**< IDCODE readout */ - uint32_t didr; /**< DIDR readout (debug capabilities) */ - uint8_t implementor; /**< DIDR Implementor readout */ + /** Debug module state. */ + struct arm_dpm dpm; + struct arm11_sc7_action *bpwp_actions; + unsigned bpwp_n; size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ - size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ - - enum arm11_debug_version - debug_version; /**< ARM debug architecture from DIDR */ - /*@}*/ + size_t free_brps; /**< Number of breakpoints allocated */ - uint32_t last_dscr; /**< Last retrieved DSCR value; - Use only for debug message generation */ + uint32_t dscr; /**< Last retrieved DSCR value. */ - bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ - - /** \name Shadow registers to save processor state */ - /*@{*/ + uint32_t saved_rdtr; + uint32_t saved_wdtr; - struct reg * reg_list; /**< target register list */ - uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */ + bool is_rdtr_saved; + bool is_wdtr_saved; - /*@}*/ - - struct arm11_register_history - reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ + bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ - size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ - size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */ + /* Per-core configurable options. + * NOTE that several of these boolean options should not exist + * once the relevant code is known to work correctly. + */ + bool memwrite_burst; + bool memwrite_error_fatal; + bool step_irq_enable; + bool hardware_step; - // GA - struct reg_cache *core_cache; + /** Configured Vector Catch Register settings. */ + uint32_t vcr; struct arm_jtag jtag_info; }; @@ -141,34 +107,6 @@ enum arm11_instructions ARM11_BYPASS = 0x1F, }; -enum arm11_dscr -{ - ARM11_DSCR_CORE_HALTED = 1 << 0, - ARM11_DSCR_CORE_RESTARTED = 1 << 1, - - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, - - ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, - ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, - ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11, - ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, - ARM11_DSCR_MODE_SELECT = 1 << 14, - ARM11_DSCR_WDTR_FULL = 1 << 29, - ARM11_DSCR_RDTR_FULL = 1 << 30, -}; - -enum arm11_cpsr -{ - ARM11_CPSR_T = 1 << 5, - ARM11_CPSR_J = 1 << 24, -}; - enum arm11_sc7 { ARM11_SC7_NULL = 0, @@ -180,10 +118,4 @@ enum arm11_sc7 ARM11_SC7_WCR0 = 112, }; -struct arm11_reg_state -{ - uint32_t def_index; - struct target * target; -}; - #endif /* ARM11_H */