X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=da084b1074ac17132feb7ad0914322e0681dba7f;hp=8b7b69c9cc3190aea41a4772c7ac3a16a553501a;hb=0c2f8b6eb8f4b379aa0c78caba73ec1ebaae8414;hpb=b7fa16eeacb368dca8862168088bc6c491f0ffb1

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 8b7b69c9cc..da084b1074 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -44,15 +44,6 @@
 #endif
 
 
-/* FIXME none of these flags should be global to all ARM11 cores!
- * Most of them shouldn't exist at all, once the code works...
- */
-static bool arm11_config_memwrite_burst = true;
-static bool arm11_config_memwrite_error_fatal = true;
-static uint32_t arm11_vcr = 0;
-static bool arm11_config_step_irq_enable = false;
-static bool arm11_config_hardware_step = false;
-
 static int arm11_step(struct target *target, int current,
 		uint32_t address, int handle_breakpoints);
 
@@ -64,14 +55,14 @@ static int arm11_step(struct target *target, int current,
 static int arm11_check_init(struct arm11_common *arm11)
 {
 	CHECK_RETVAL(arm11_read_DSCR(arm11));
-	LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 
 	if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
 	{
+		LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 		LOG_DEBUG("Bringing target into debug mode");
 
 		arm11->dscr |= DSCR_HALT_DBG_MODE;
-		arm11_write_DSCR(arm11, arm11->dscr);
+		CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
 
 		/* add further reset initialization here */
 
@@ -94,7 +85,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 			arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
 		}
 
-		arm11_sc7_clear_vbw(arm11);
+		CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 	}
 
 	return ERROR_OK;
@@ -132,7 +123,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 1);
 		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 2);
 
-		arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+		arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 
 	}
 
@@ -142,7 +133,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 	 * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
 	 * for executing instructions via ITR.
 	 */
-	arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
+	CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
 
 
 	/* From the spec:
@@ -184,7 +175,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 	 */
 	retval = arm_dpm_read_current_registers(&arm11->dpm);
 	if (retval != ERROR_OK)
-		LOG_ERROR("DPM REG READ -- fail %d", retval);
+		LOG_ERROR("DPM REG READ -- fail");
 
 	retval = arm11_run_instr_data_prepare(arm11);
 	if (retval != ERROR_OK)
@@ -300,14 +291,14 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 	/* restore CPSR, PC, and R0 ... after flushing any modified
 	 * registers.
 	 */
-	retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
+	CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
 
-	retval = arm11_bpwp_flush(arm11);
+	CHECK_RETVAL(arm11_bpwp_flush(arm11));
 
 	register_cache_invalidate(arm11->arm.core_cache);
 
 	/* restore DSCR */
-	arm11_write_DSCR(arm11, arm11->dscr);
+	CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
 
 	/* maybe restore rDTR */
 	if (arm11->is_rdtr_saved)
@@ -326,7 +317,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 		arm11_setup_field(arm11,  1, &Ready,	NULL, chain5_fields + 1);
 		arm11_setup_field(arm11,  1, &Valid,	NULL, chain5_fields + 2);
 
-		arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+		arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 	}
 
 	/* now processor is ready to RESTART */
@@ -448,7 +439,7 @@ static int arm11_halt(struct target *target)
 
 	enum target_state old_state	= target->state;
 
-	arm11_debug_entry(arm11);
+	CHECK_RETVAL(arm11_debug_entry(arm11));
 
 	CHECK_RETVAL(
 		target_call_event_callbacks(target,
@@ -460,7 +451,7 @@ static int arm11_halt(struct target *target)
 static uint32_t
 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 {
-	void *value = arm11->arm.core_cache->reg_list[15].value;
+	void *value = arm11->arm.pc->value;
 
 	if (!current)
 		buf_set_u32(value, 0, 32, address);
@@ -493,7 +484,7 @@ static int arm11_resume(struct target *target, int current,
 	LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 
 	/* clear breakpoints/watchpoints and VCR*/
-	arm11_sc7_clear_vbw(arm11);
+	CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 
 	if (!debug_execution)
 		target_free_all_working_areas(target);
@@ -529,7 +520,7 @@ static int arm11_resume(struct target *target, int current,
 			brp[1].address	= ARM11_SC7_BCR0 + brp_num;
 			brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 
-			arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
+			CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 
 			LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 					bp->address);
@@ -537,12 +528,12 @@ static int arm11_resume(struct target *target, int current,
 			brp_num++;
 		}
 
-		if (arm11_vcr)
-			arm11_sc7_set_vcr(arm11, arm11_vcr);
+		if (arm11->vcr)
+			CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 	}
 
 	/* activate all watchpoints and breakpoints */
-	arm11_leave_debug_state(arm11, true);
+	CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
 
 	arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
@@ -614,14 +605,14 @@ static int arm11_step(struct target *target, int current,
 	if ((next_instruction & 0xFFF00070) == 0xe1200070)
 	{
 		address = arm11_nextpc(arm11, 0, address + 4);
-		LOG_DEBUG("Skipping BKPT");
+		LOG_DEBUG("Skipping BKPT %08" PRIx32, address);
 	}
 	/* skip over Wait for interrupt / Standby */
 	/* mcr	15, 0, r?, cr7, cr0, {4} */
 	else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 	{
 		address = arm11_nextpc(arm11, 0, address + 4);
-		LOG_DEBUG("Skipping WFI");
+		LOG_DEBUG("Skipping WFI %08" PRIx32, address);
 	}
 	/* ignore B to self */
 	else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
@@ -646,7 +637,7 @@ static int arm11_step(struct target *target, int current,
 		brp[1].write	= 1;
 		brp[1].address	= ARM11_SC7_BCR0;
 
-		if (arm11_config_hardware_step)
+		if (arm11->hardware_step)
 		{
 			/* Hardware single stepping ("instruction address
 			 * mismatch") is used if enabled.  It's not quite
@@ -690,7 +681,7 @@ static int arm11_step(struct target *target, int current,
 		/* resume */
 
 
-		if (arm11_config_step_irq_enable)
+		if (arm11->step_irq_enable)
 			/* this disable should be redundant ... */
 			arm11->dscr &= ~DSCR_INT_DIS;
 		else
@@ -734,7 +725,7 @@ static int arm11_step(struct target *target, int current,
 		}
 
 		/* clear breakpoint */
-		arm11_sc7_clear_vbw(arm11);
+		CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
 
 		/* save state */
 		CHECK_RETVAL(arm11_debug_entry(arm11));
@@ -756,8 +747,8 @@ static int arm11_assert_reset(struct target *target)
 	struct arm11_common *arm11 = target_to_arm11(target);
 
 	/* optionally catch reset vector */
-	if (target->reset_halt && !(arm11_vcr & 1))
-		arm11_sc7_set_vcr(arm11, arm11_vcr | 1);
+	if (target->reset_halt && !(arm11->vcr & 1))
+		CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
 
 	/* Issue some kind of warm reset. */
 	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
@@ -804,7 +795,7 @@ static int arm11_deassert_reset(struct target *target)
 	 */
 	jtag_add_tlr();
 
-	retval = arm11_poll(target);
+	CHECK_RETVAL(arm11_poll(target));
 
 	if (target->reset_halt) {
 		if (target->state != TARGET_HALTED) {
@@ -816,8 +807,8 @@ static int arm11_deassert_reset(struct target *target)
 	}
 
 	/* maybe restore vector catch config */
-	if (target->reset_halt && !(arm11_vcr & 1))
-		arm11_sc7_set_vcr(arm11, arm11_vcr);
+	if (target->reset_halt && !(arm11->vcr & 1))
+		CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
 
 	return ERROR_OK;
 }
@@ -872,12 +863,12 @@ static int arm11_read_memory_inner(struct target *target,
 		{
 			/* ldrb    r1, [r0], #1 */
 			/* ldrb    r1, [r0] */
-			arm11_run_instr_no_data1(arm11,
-					!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
+			CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+					!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
 
 			uint32_t res;
 			/* MCR p14,0,R1,c0,c5,0 */
-			arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+			CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 
 			*buffer++ = res;
 		}
@@ -891,13 +882,13 @@ static int arm11_read_memory_inner(struct target *target,
 			for (size_t i = 0; i < count; i++)
 			{
 				/* ldrh    r1, [r0], #2 */
-				arm11_run_instr_no_data1(arm11,
-					!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
+				CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+					!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
 
 				uint32_t res;
 
 				/* MCR p14,0,R1,c0,c5,0 */
-				arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
+				CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 
 				uint16_t svalue = res;
 				memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
@@ -910,11 +901,11 @@ static int arm11_read_memory_inner(struct target *target,
 		{
 		uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 		/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
-		uint32_t *words = (uint32_t *)buffer;
+		uint32_t *words = (uint32_t *)(void *)buffer;
 
 		/* LDC p14,c5,[R0],#4 */
 		/* LDC p14,c5,[R0] */
-		arm11_run_instr_data_from_core(arm11, instr, words, count);
+		CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
 		break;
 		}
 	}
@@ -934,7 +925,7 @@ static int arm11_read_memory(struct target *target, uint32_t address, uint32_t s
 */
 static int arm11_write_memory_inner(struct target *target,
 		uint32_t address, uint32_t size,
-		uint32_t count, uint8_t *buffer,
+		uint32_t count, const uint8_t *buffer,
 		bool no_increment)
 {
 	int retval;
@@ -966,7 +957,7 @@ static int arm11_write_memory_inner(struct target *target,
 	 * now exercise both burst and non-burst code paths with the
 	 * default settings, increasing code coverage.
 	 */
-	bool burst = arm11_config_memwrite_burst && (count > 1);
+	bool burst = arm11->memwrite_burst && (count > 1);
 
 	switch (size)
 	{
@@ -1032,7 +1023,7 @@ static int arm11_write_memory_inner(struct target *target,
 		uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
 
 		/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
-		uint32_t *words = (uint32_t*)buffer;
+		uint32_t *words = (uint32_t*)(void *)buffer;
 
 		/* "burst" here just means trusting each instruction executes
 		 * fully before we run the next one:  per-word roundtrips, to
@@ -1071,7 +1062,7 @@ static int arm11_write_memory_inner(struct target *target,
 			if (burst)
 				LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
 
-			if (arm11_config_memwrite_error_fatal)
+			if (arm11->memwrite_error_fatal)
 				return ERROR_FAIL;
 		}
 	}
@@ -1081,7 +1072,7 @@ static int arm11_write_memory_inner(struct target *target,
 
 static int arm11_write_memory(struct target *target,
 		uint32_t address, uint32_t size,
-		uint32_t count, uint8_t *buffer)
+		uint32_t count, const uint8_t *buffer)
 {
 	/* pointer increment matters only for multi-unit writes ...
 	 * not e.g. to a "reset the chip" controller.
@@ -1092,7 +1083,7 @@ static int arm11_write_memory(struct target *target,
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 static int arm11_bulk_write_memory(struct target *target,
-		uint32_t address, uint32_t count, uint8_t *buffer)
+		uint32_t address, uint32_t count, const uint8_t *buffer)
 {
 	if (target->state != TARGET_HALTED)
 	{
@@ -1171,6 +1162,9 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	arm11->jtag_info.cur_scan_chain = ~0;	/* invalid/unknown */
 	arm11->jtag_info.intest_instr = ARM11_INTEST;
 
+	arm11->memwrite_burst = true;
+	arm11->memwrite_error_fatal = true;
+
 	return ERROR_OK;
 }
 
@@ -1200,7 +1194,7 @@ static int arm11_examine(struct target *target)
 
 	arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
 
-	arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
+	arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
 
 	/* check DIDR */
 
@@ -1213,7 +1207,7 @@ static int arm11_examine(struct target *target)
 	arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
 	arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
 
-	arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
+	arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
 
 	CHECK_RETVAL(jtag_execute_queue());
 
@@ -1231,6 +1225,7 @@ static int arm11_examine(struct target *target)
 		break;
 	case 0x7B76:
 		arm11->arm.core_type = ARM_MODE_MON;
+		/* NOTE: could default arm11->hardware_step to true */
 		type = "ARM1176";
 		break;
 	default:
@@ -1270,14 +1265,14 @@ static int arm11_examine(struct target *target)
 	 * want to know if this core supports Secure Monitor mode.
 	 */
 	if (!target_was_examined(target))
-		retval = arm11_dpm_init(arm11, didr);
+		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
 
 	/* ETM on ARM11 still uses original scanchain 6 access mode */
 	if (arm11->arm.etm && !target_was_examined(target)) {
 		*register_get_last_cache_p(&target->reg_cache) =
 			etm_build_reg_cache(target, &arm11->jtag_info,
 					arm11->arm.etm);
-		retval = etm_setup(target);
+		CHECK_RETVAL(etm_setup(target));
 	}
 
 	target_set_examined(target);
@@ -1286,38 +1281,41 @@ static int arm11_examine(struct target *target)
 }
 
 
-/* FIXME all these BOOL_WRAPPER things should be modifying
- * per-instance state, not shared state; ditto the vector
- * catch register support.  Scan chains with multiple cores
- * should be able to say "work with this core like this,
- * that core like that".  Example, ARM11 MPCore ...
- */
-
 #define ARM11_BOOL_WRAPPER(name, print_name)	\
-		COMMAND_HANDLER(arm11_handle_bool_##name) \
-		{ \
-			return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
-					&arm11_config_##name, print_name); \
-		}
+	COMMAND_HANDLER(arm11_handle_bool_##name) \
+	{ \
+		struct target *target = get_current_target(CMD_CTX); \
+		struct arm11_common *arm11 = target_to_arm11(target); \
+		\
+		return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
+				&arm11->name, print_name); \
+	}
 
 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
 
+/* REVISIT handle the VCR bits like other ARMs:  use symbols for
+ * input and output values.
+ */
+
 COMMAND_HANDLER(arm11_handle_vcr)
 {
+	struct target *target = get_current_target(CMD_CTX);
+	struct arm11_common *arm11 = target_to_arm11(target);
+
 	switch (CMD_ARGC) {
 	case 0:
 		break;
 	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
 		break;
 	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
+	LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
 	return ERROR_OK;
 }
 
@@ -1357,6 +1355,7 @@ static const struct command_registration arm11_any_command_handlers[] = {
 		.name = "memwrite",
 		.mode = COMMAND_ANY,
 		.help = "memwrite command group",
+		.usage = "",
 		.chain = arm11_mw_command_handlers,
 	},
 	{
@@ -1376,6 +1375,7 @@ static const struct command_registration arm11_any_command_handlers[] = {
 	},
 	COMMAND_REGISTRATION_DONE
 };
+
 static const struct command_registration arm11_command_handlers[] = {
 	{
 		.chain = arm_command_handlers,
@@ -1387,6 +1387,7 @@ static const struct command_registration arm11_command_handlers[] = {
 		.name = "arm11",
 		.mode = COMMAND_ANY,
 		.help = "ARM11 command group",
+		.usage = "",
 		.chain = arm11_any_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE