X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=943ab8ae804d95059cea0a179116ed12d22c3d4e;hp=1a3e9797b3293f410839f5fc0ac70d6782e48f73;hb=a0edb8a328ceea23186ab74c941454fb146c9a48;hpb=1d29440a9c6a7ceb933a4aa407387cc7d9f8bdb2 diff --git a/src/target/arm11.c b/src/target/arm11.c index 1a3e9797b3..943ab8ae80 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -30,7 +30,7 @@ #include "breakpoints.h" #include "arm11_dbgtap.h" #include "arm_simulator.h" -#include "time_support.h" +#include #include "target_type.h" #include "algorithm.h" #include "register.h" @@ -40,96 +40,50 @@ #define _DEBUG_INSTRUCTION_EXECUTION_ #endif + +/* FIXME none of these flags should be global to all ARM11 cores! + * Most of them shouldn't exist at all, once the code works... + */ static bool arm11_config_memwrite_burst = true; static bool arm11_config_memwrite_error_fatal = true; static uint32_t arm11_vcr = 0; static bool arm11_config_step_irq_enable = false; static bool arm11_config_hardware_step = false; -enum arm11_regtype -{ - /* debug regs */ - ARM11_REGISTER_DSCR, - ARM11_REGISTER_WDTR, - ARM11_REGISTER_RDTR, -}; - - -struct arm11_reg_defs -{ - char * name; - uint32_t num; - int gdb_num; - enum arm11_regtype type; -}; - -/* update arm11_regcache_ids when changing this */ -static const struct arm11_reg_defs arm11_reg_defs[] = -{ - /* Debug Registers */ - {"dscr", 0, -1, ARM11_REGISTER_DSCR}, - {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, - {"rdtr", 0, -1, ARM11_REGISTER_RDTR}, -}; - -enum arm11_regcache_ids -{ - ARM11_RC_DSCR, - ARM11_RC_WDTR, - ARM11_RC_RDTR, - - ARM11_RC_MAX, -}; - -static int arm11_on_enter_debug_state(struct arm11_common *arm11); static int arm11_step(struct target *target, int current, uint32_t address, int handle_breakpoints); -/* helpers */ -static int arm11_build_reg_cache(struct target *target); -static int arm11_set_reg(struct reg *reg, uint8_t *buf); -static int arm11_get_reg(struct reg *reg); /** Check and if necessary take control of the system * * \param arm11 Target state variable. - * \param dscr If the current DSCR content is - * available a pointer to a word holding the - * DSCR can be passed. Otherwise use NULL. */ -static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr) +static int arm11_check_init(struct arm11_common *arm11) { - uint32_t dscr_local_tmp_copy; + CHECK_RETVAL(arm11_read_DSCR(arm11)); + LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); - if (!dscr) - { - dscr = &dscr_local_tmp_copy; - - CHECK_RETVAL(arm11_read_DSCR(arm11, dscr)); - } - - if (!(*dscr & ARM11_DSCR_MODE_SELECT)) + if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) { LOG_DEBUG("Bringing target into debug mode"); - *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ - arm11_write_DSCR(arm11, *dscr); + arm11->dscr |= DSCR_HALT_DBG_MODE; + arm11_write_DSCR(arm11, arm11->dscr); /* add further reset initialization here */ arm11->simulate_reset_on_next_halt = true; - if (*dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) { /** \todo TODO: this needs further scrutiny because - * arm11_on_enter_debug_state() never gets properly called. + * arm11_debug_entry() never gets called. (WHY NOT?) * As a result we don't read the actual register states from * the target. */ arm11->arm.target->state = TARGET_HALTED; - arm11->arm.target->debug_reason = - arm11_get_DSCR_debug_reason(*dscr); + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); } else { @@ -143,38 +97,26 @@ static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr) return ERROR_OK; } - - -#define R(x) \ - (arm11->reg_values[ARM11_RC_##x]) - -/** Save processor state. - * - * This is called when the HALT instruction has succeeded - * or on other occasions that stop the processor. - * - */ -static int arm11_on_enter_debug_state(struct arm11_common *arm11) +/** + * Save processor state. This is called after a HALT instruction + * succeeds, and on other occasions the processor enters debug mode + * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr. + */ +static int arm11_debug_entry(struct arm11_common *arm11) { int retval; + arm11->arm.target->state = TARGET_HALTED; + arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr); + /* REVISIT entire cache should already be invalid !!! */ register_cache_invalidate(arm11->arm.core_cache); - for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) - { - arm11->reg_list[i].valid = 1; - arm11->reg_list[i].dirty = 0; - } - /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ - /* Save DSCR */ - CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR))); - - /* Save wDTR */ - - if (R(DSCR) & ARM11_DSCR_WDTR_FULL) + /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */ + arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL); + if (arm11->is_wdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); @@ -182,29 +124,22 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) struct scan_field chain5_fields[3]; - arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); + arm11_setup_field(arm11, 32, NULL, + &arm11->saved_wdtr, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); - } - else - { - arm11->reg_list[ARM11_RC_WDTR].valid = 0; - } + } - /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE + /* DSCR: set the Execute ARM instruction enable bit. * * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", - * but not to issue ITRs. ARM1136 seems to require this to issue - * ITR's as well... + * but not to issue ITRs(?). The ARMv7 arch spec says it's required + * for executing instructions via ITR. */ - uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; - - /* this executes JTAG queue: */ - - arm11_write_DSCR(arm11, new_dscr); + arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr); /* From the spec: @@ -252,21 +187,16 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) if (retval != ERROR_OK) return retval; - /* maybe save rDTR */ - - /* check rDTRfull in DSCR */ - - if (R(DSCR) & ARM11_DSCR_RDTR_FULL) + /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */ + arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL); + if (arm11->is_rdtr_saved) { /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ - retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); + retval = arm11_run_instr_data_from_core_via_r0(arm11, + 0xEE100E15, &arm11->saved_rdtr); if (retval != ERROR_OK) return retval; } - else - { - arm11->reg_list[ARM11_RC_RDTR].valid = 0; - } /* REVISIT Now that we've saved core state, there's may also * be MMU and cache state to care about ... @@ -316,11 +246,9 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) /* spec says clear wDTR and rDTR; we assume they are clear as otherwise our programming would be sloppy */ { - uint32_t DSCR; + CHECK_RETVAL(arm11_read_DSCR(arm11)); - CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR)); - - if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) + if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) { /* The wDTR/rDTR two registers that are used to send/receive data to/from @@ -329,20 +257,22 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) registers hold data that was written by one side (CPU or JTAG) and not read out by the other side. */ - LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); + LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", + (unsigned) arm11->dscr); return ERROR_FAIL; } } /* maybe restore original wDTR */ - if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) + if (arm11->is_wdtr_saved) { retval = arm11_run_instr_data_prepare(arm11); if (retval != ERROR_OK) return retval; /* MCR p14,0,R0,c0,c5,0 */ - retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); + retval = arm11_run_instr_data_to_core_via_r0(arm11, + 0xee000e15, arm11->saved_wdtr); if (retval != ERROR_OK) return retval; @@ -356,15 +286,15 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) */ retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp); + retval = arm11_bpwp_flush(arm11); + register_cache_invalidate(arm11->arm.core_cache); /* restore DSCR */ - - arm11_write_DSCR(arm11, R(DSCR)); + arm11_write_DSCR(arm11, arm11->dscr); /* maybe restore rDTR */ - - if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) + if (arm11->is_rdtr_saved) { arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); @@ -375,7 +305,8 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) uint8_t Ready = 0; /* ignored */ uint8_t Valid = 0; /* ignored */ - arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0); + arm11_setup_field(arm11, 32, &arm11->saved_rdtr, + NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); @@ -392,24 +323,17 @@ static int arm11_poll(struct target *target) { int retval; struct arm11_common *arm11 = target_to_arm11(target); - uint32_t dscr; - - CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); - LOG_DEBUG("DSCR %08" PRIx32 "", dscr); + CHECK_RETVAL(arm11_check_init(arm11)); - CHECK_RETVAL(arm11_check_init(arm11, &dscr)); - - if (dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) { if (target->state != TARGET_HALTED) { enum target_state old_state = target->state; LOG_DEBUG("enter TARGET_HALTED"); - target->state = TARGET_HALTED; - target->debug_reason = arm11_get_DSCR_debug_reason(dscr); - retval = arm11_on_enter_debug_state(arm11); + retval = arm11_debug_entry(arm11); if (retval != ERROR_OK) return retval; @@ -473,14 +397,13 @@ static int arm11_halt(struct target *target) CHECK_RETVAL(jtag_execute_queue()); - uint32_t dscr; - int i = 0; + while (1) { - CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + CHECK_RETVAL(arm11_read_DSCR(arm11)); - if (dscr & ARM11_DSCR_CORE_HALTED) + if (arm11->dscr & DSCR_CORE_HALTED) break; @@ -500,12 +423,9 @@ static int arm11_halt(struct target *target) i++; } - arm11_on_enter_debug_state(arm11); - enum target_state old_state = target->state; - target->state = TARGET_HALTED; - target->debug_reason = arm11_get_DSCR_debug_reason(dscr); + arm11_debug_entry(arm11); CHECK_RETVAL( target_call_event_callbacks(target, @@ -595,7 +515,8 @@ static int arm11_resume(struct target *target, int current, brp_num++; } - arm11_sc7_set_vcr(arm11, arm11_vcr); + if (arm11_vcr) + arm11_sc7_set_vcr(arm11, arm11_vcr); } arm11_leave_debug_state(arm11, handle_breakpoints); @@ -607,13 +528,11 @@ static int arm11_resume(struct target *target, int current, int i = 0; while (1) { - uint32_t dscr; - - CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + CHECK_RETVAL(arm11_read_DSCR(arm11)); - LOG_DEBUG("DSCR %08" PRIx32 "", dscr); + LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr); - if (dscr & ARM11_DSCR_CORE_RESTARTED) + if (arm11->dscr & DSCR_CORE_RESTARTED) break; @@ -633,20 +552,12 @@ static int arm11_resume(struct target *target, int current, i++; } + target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) - { - target->state = TARGET_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_RUNNING; else - { - target->state = TARGET_DEBUG_RUNNING; - target->debug_reason = DBG_REASON_NOTHALTED; - - CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); - } + target->state = TARGET_DEBUG_RUNNING; + CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED)); return ERROR_OK; } @@ -757,9 +668,10 @@ static int arm11_step(struct target *target, int current, if (arm11_config_step_irq_enable) - R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */ + /* this disable should be redundant ... */ + arm11->dscr &= ~DSCR_INT_DIS; else - R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE; + arm11->dscr |= DSCR_INT_DIS; CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints)); @@ -770,16 +682,16 @@ static int arm11_step(struct target *target, int current, /* wait for halt */ int i = 0; + while (1) { - uint32_t dscr; - - CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); + const uint32_t mask = DSCR_CORE_RESTARTED + | DSCR_CORE_HALTED; - LOG_DEBUG("DSCR %08" PRIx32 "e", dscr); + CHECK_RETVAL(arm11_read_DSCR(arm11)); + LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr); - if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == - (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) + if ((arm11->dscr & mask) == mask) break; long long then = 0; @@ -802,15 +714,14 @@ static int arm11_step(struct target *target, int current, arm11_sc7_clear_vbw(arm11); /* save state */ - CHECK_RETVAL(arm11_on_enter_debug_state(arm11)); + CHECK_RETVAL(arm11_debug_entry(arm11)); - /* restore default state */ - R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; + /* restore default state */ + arm11->dscr &= ~DSCR_INT_DIS; } - // target->state = TARGET_HALTED; - target->debug_reason = DBG_REASON_SINGLESTEP; + target->debug_reason = DBG_REASON_SINGLESTEP; CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED)); @@ -822,7 +733,7 @@ static int arm11_assert_reset(struct target *target) int retval; struct arm11_common *arm11 = target_to_arm11(target); - retval = arm11_check_init(arm11, NULL); + retval = arm11_check_init(arm11); if (retval != ERROR_OK) return retval; @@ -1225,7 +1136,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp) arm11->jtag_info.tap = target->tap; arm11->jtag_info.scann_size = 5; arm11->jtag_info.scann_instr = ARM11_SCAN_N; - /* cur_scan_chain == 0 */ + arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */ arm11->jtag_info.intest_instr = ARM11_INTEST; return ERROR_OK; @@ -1235,12 +1146,7 @@ static int arm11_init_target(struct command_context *cmd_ctx, struct target *target) { /* Initialize anything we can set up without talking to the target */ - - /* REVISIT do we really want such a debug-registers-only cache? - * If we do, it should probably be handled purely by the DPM code, - * so it works identically on the v7a/v7r cores. - */ - return arm11_build_reg_cache(target); + return ERROR_OK; } /* talk to the target and set things up */ @@ -1308,7 +1214,6 @@ static int arm11_examine(struct target *target) } arm11->brp = ((didr >> 24) & 0x0F) + 1; - arm11->wrp = ((didr >> 28) & 0x0F) + 1; /** \todo TODO: reserve one brp slot if we allow breakpoints during step */ arm11->free_brps = arm11->brp; @@ -1321,7 +1226,7 @@ static int arm11_examine(struct target *target) * as suggested by the spec. */ - retval = arm11_check_init(arm11, NULL); + retval = arm11_check_init(arm11); if (retval != ERROR_OK) return retval; @@ -1345,117 +1250,6 @@ static int arm11_examine(struct target *target) } -/** Load a register that is marked !valid in the register cache */ -static int arm11_get_reg(struct reg *reg) -{ - struct arm11_reg_state *r = reg->arch_info; - struct target *target = r->target; - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */ - -#if 0 - struct arm11_common *arm11 = target_to_arm11(target); - const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; -#endif - - return ERROR_OK; -} - -/** Change a value in the register cache */ -static int arm11_set_reg(struct reg *reg, uint8_t *buf) -{ - struct arm11_reg_state *r = reg->arch_info; - struct target *target = r->target; - struct arm11_common *arm11 = target_to_arm11(target); -// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; - - arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); - reg->valid = 1; - reg->dirty = 1; - - return ERROR_OK; -} - -static const struct reg_arch_type arm11_reg_type = { - .get = arm11_get_reg, - .set = arm11_set_reg, -}; - -static int arm11_build_reg_cache(struct target *target) -{ - struct arm11_common *arm11 = target_to_arm11(target); - struct reg_cache *cache; - struct reg *reg_list; - struct arm11_reg_state *arm11_reg_states; - - cache = calloc(1, sizeof *cache); - reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list); - arm11_reg_states = calloc(ARM11_REGCACHE_COUNT, - sizeof *arm11_reg_states); - if (!cache || !reg_list || !arm11_reg_states) { - free(cache); - free(reg_list); - free(arm11_reg_states); - return ERROR_FAIL; - } - - arm11->reg_list = reg_list; - - /* build cache for some of the debug registers */ - cache->name = "arm11 debug registers"; - cache->reg_list = reg_list; - cache->num_regs = ARM11_REGCACHE_COUNT; - - struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - (*cache_p) = cache; - - arm11->core_cache = cache; - - size_t i; - - /* Not very elegant assertion */ - if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) || - ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) || - ARM11_REGCACHE_COUNT != ARM11_RC_MAX) - { - LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)", - ARM11_REGCACHE_COUNT, - (unsigned) ARRAY_SIZE(arm11->reg_values), - (unsigned) ARRAY_SIZE(arm11_reg_defs), - ARM11_RC_MAX); - /* FIXME minimally, use a build_bug_on(X) mechanism; - * runtime exit() here is bad! - */ - exit(-1); - } - - for (i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - struct reg * r = reg_list + i; - const struct arm11_reg_defs * rd = arm11_reg_defs + i; - struct arm11_reg_state * rs = arm11_reg_states + i; - - r->name = rd->name; - r->size = 32; - r->value = (uint8_t *)(arm11->reg_values + i); - r->dirty = 0; - r->valid = 0; - r->type = &arm11_reg_type; - r->arch_info = rs; - - rs->def_index = i; - rs->target = target; - } - - return ERROR_OK; -} - /* FIXME all these BOOL_WRAPPER things should be modifying * per-instance state, not shared state; ditto the vector * catch register support. Scan chains with multiple cores