X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=7f92ce470d690cbb6ce6401aca69e476c683361d;hp=45deb60c5ec2d5a99e636249ec87061b09c97df2;hb=ae17ce23eb7bf4c0892c609f0a49daa8cd63d8c5;hpb=350f608256d167851a13f6b976c465b54f1056ad diff --git a/src/target/arm11.c b/src/target/arm11.c index 45deb60c5e..7f92ce470d 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -27,6 +27,9 @@ #endif #include "arm11.h" +#include "armv4_5.h" +#include "arm_simulator.h" +#include "target_type.h" #if 0 @@ -49,9 +52,10 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11); bool arm11_config_memwrite_burst = true; bool arm11_config_memwrite_error_fatal = true; -u32 arm11_vcr = 0; +uint32_t arm11_vcr = 0; bool arm11_config_memrw_no_increment = false; bool arm11_config_step_irq_enable = false; +bool arm11_config_hardware_step = false; #define ARM11_HANDLER(x) \ .x = arm11_##x @@ -131,7 +135,7 @@ enum arm11_regtype typedef struct arm11_reg_defs_s { char * name; - u32 num; + uint32_t num; int gdb_num; enum arm11_regtype type; } arm11_reg_defs_t; @@ -287,14 +291,14 @@ enum arm11_regcache_ids #define ARM11_GDB_REGISTER_COUNT 26 -u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; reg_t arm11_gdb_dummy_fp_reg = { "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 }; -u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; reg_t arm11_gdb_dummy_fps_reg = { @@ -310,11 +314,11 @@ reg_t arm11_gdb_dummy_fps_reg = * available a pointer to a word holding the * DSCR can be passed. Otherwise use NULL. */ -int arm11_check_init(arm11_common_t * arm11, u32 * dscr) +int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) { FNC_INFO; - u32 dscr_local_tmp_copy; + uint32_t dscr_local_tmp_copy; if (!dscr) { @@ -407,7 +411,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs ARM1136 seems to require this to issue ITR's as well */ - u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; + uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; /* this executes JTAG queue: */ @@ -429,7 +433,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) /* mcr 15, 0, r0, cr7, cr10, {4} */ arm11_run_instr_no_data1(arm11, 0xee070f9a); - u32 dscr = arm11_read_DSCR(arm11); + uint32_t dscr = arm11_read_DSCR(arm11); LOG_DEBUG("DRAIN, DSCR %08x", dscr); @@ -530,18 +534,18 @@ void arm11_dump_reg_changes(arm11_common_t * arm11) if (!arm11->reg_list[i].valid) { if (arm11->reg_history[i].valid) - LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value); + LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value); } else { if (arm11->reg_history[i].valid) { if (arm11->reg_history[i].value != arm11->reg_values[i]) - LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); + LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); } else { - LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); + LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); } } } @@ -578,13 +582,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11) /* spec says clear wDTR and rDTR; we assume they are clear as otherwise our programming would be sloppy */ { - u32 DSCR; + uint32_t DSCR; CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR)); if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) { - LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR); + LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); } } @@ -629,8 +633,8 @@ int arm11_leave_debug_state(arm11_common_t * arm11) scan_field_t chain5_fields[3]; - u8 Ready = 0; /* ignored */ - u8 Valid = 0; /* ignored */ + uint8_t Ready = 0; /* ignored */ + uint8_t Valid = 0; /* ignored */ arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); @@ -667,11 +671,11 @@ int arm11_poll(struct target_s *target) if (arm11->trst_active) return ERROR_OK; - u32 dscr; + uint32_t dscr; CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); - LOG_DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08" PRIx32 "", dscr); CHECK_RETVAL(arm11_check_init(arm11, &dscr)); @@ -707,8 +711,8 @@ int arm11_arch_state(struct target_s *target) { arm11_common_t * arm11 = target->arch_info; - LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x", - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name, + LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, R(CPSR), R(PC)); @@ -716,7 +720,7 @@ int arm11_arch_state(struct target_s *target) } /* target request support */ -int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer) +int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer) { FNC_INFO_NOTIMPLEMENTED; @@ -731,7 +735,7 @@ int arm11_halt(struct target_s *target) arm11_common_t * arm11 = target->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state == TARGET_UNKNOWN) { @@ -754,7 +758,7 @@ int arm11_halt(struct target_s *target) CHECK_RETVAL(jtag_execute_queue()); - u32 dscr; + uint32_t dscr; while (1) { @@ -778,7 +782,7 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } -int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) +int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { FNC_INFO; @@ -788,7 +792,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b arm11_common_t * arm11 = target->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state != TARGET_HALTED) @@ -800,7 +804,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b if (!current) R(PC) = address; - LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : ""); + LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); /* clear breakpoints/watchpoints and VCR*/ arm11_sc7_clear_vbw(arm11); @@ -816,7 +820,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b { if (bp->address == R(PC)) { - LOG_DEBUG("must step over %08x", bp->address); + LOG_DEBUG("must step over %08" PRIx32 "", bp->address); arm11_step(target, 1, 0, 0); break; } @@ -839,7 +843,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b arm11_sc7_run(arm11, brp, asizeof(brp)); - LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address); + LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address); brp_num++; } @@ -855,11 +859,11 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b while (1) { - u32 dscr; + uint32_t dscr; CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); - LOG_DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08" PRIx32 "", dscr); if (dscr & ARM11_DSCR_CORE_RESTARTED) break; @@ -883,12 +887,99 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b return ERROR_OK; } -int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints) + +static int armv4_5_to_arm11(int reg) +{ + if (reg < 16) + return reg; + switch (reg) + { + case ARMV4_5_CPSR: + return ARM11_RC_CPSR; + case 16: + /* FIX!!! handle thumb better! */ + return ARM11_RC_CPSR; + default: + LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg); + exit(-1); + } +} + + +static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + reg=armv4_5_to_arm11(reg); + + return buf_get_u32(arm11->reg_list[reg].value, 0, 32); +} + +static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + reg=armv4_5_to_arm11(reg); + + buf_set_u32(arm11->reg_list[reg].value, 0, 32, value); +} + +static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) +{ + arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits); +} + +static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim) +{ +// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement thumb for arm11 */ + return ARMV4_5_STATE_ARM; +} + +static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +{ +// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement thumb for arm11 */ + LOG_ERROR("Not implemetned!"); +} + + +static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim) +{ + //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + + /* FIX!!!! we should implement something that returns the current mode here!!! */ + return ARMV4_5_MODE_USR; +} + +static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc) +{ + struct arm_sim_interface sim; + + sim.user_data=target->arch_info; + sim.get_reg=&arm11_sim_get_reg; + sim.set_reg=&arm11_sim_set_reg; + sim.get_reg_mode=&arm11_sim_get_reg; + sim.set_reg_mode=&arm11_sim_set_reg; + sim.get_cpsr=&arm11_sim_get_cpsr; + sim.get_mode=&arm11_sim_get_mode; + sim.get_state=&arm11_sim_get_state; + sim.set_state=&arm11_sim_set_state; + + return arm_simulate_step_core(target, dry_run_pc, &sim); + +} + +int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { FNC_INFO; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); if (target->state != TARGET_HALTED) { @@ -901,11 +992,12 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre if (!current) R(PC) = address; - LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : ""); + LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); + /** \todo TODO: Thumb not supported here */ - u32 next_instruction; + uint32_t next_instruction; CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction)); @@ -946,10 +1038,30 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0; - brp[0].value = R(PC); brp[1].write = 1; brp[1].address = ARM11_SC7_BCR0; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + + if (arm11_config_hardware_step) + { + /* hardware single stepping be used if possible or is it better to + * always use the same code path? Hardware single stepping is not supported + * on all hardware + */ + brp[0].value = R(PC); + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + } else + { + /* sets a breakpoint on the next PC(calculated by simulation), + */ + uint32_t next_pc; + int retval; + retval = arm11_simulate_step(target, &next_pc); + if (retval != ERROR_OK) + return retval; + + brp[0].value = next_pc; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); + } CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp))); @@ -974,11 +1086,11 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre while (1) { - u32 dscr; + uint32_t dscr; CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); - LOG_DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08" PRIx32 "e", dscr); if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) @@ -1034,7 +1146,7 @@ int arm11_deassert_reset(struct target_s *target) #if 0 LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name ); + target_state_name(target)); /* deassert reset lines */ @@ -1089,9 +1201,9 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of */ -int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */ + /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ FNC_INFO; @@ -1101,7 +1213,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, return ERROR_TARGET_NOT_HALTED; } - LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); arm11_common_t * arm11 = target->arch_info; @@ -1123,7 +1235,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, arm11_run_instr_no_data1(arm11, !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000); - u32 res; + uint32_t res; /* MCR p14,0,R1,c0,c5,0 */ arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); @@ -1142,13 +1254,13 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, arm11_run_instr_no_data1(arm11, !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0); - u32 res; + uint32_t res; /* MCR p14,0,R1,c0,c5,0 */ arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); - u16 svalue = res; - memcpy(buffer + count * sizeof(u16), &svalue, sizeof(u16)); + uint16_t svalue = res; + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); } break; @@ -1156,9 +1268,9 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, case 4: { - u32 instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; - /** \todo TODO: buffer cast to u32* causes alignment warnings */ - u32 *words = (u32 *)buffer; + uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t *)buffer; /* LDC p14,c5,[R0],#4 */ /* LDC p14,c5,[R0] */ @@ -1172,7 +1284,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, return ERROR_OK; } -int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { FNC_INFO; @@ -1182,7 +1294,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count return ERROR_TARGET_NOT_HALTED; } - LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); + LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); arm11_common_t * arm11 = target->arch_info; @@ -1217,8 +1329,8 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count for (size_t i = 0; i < count; i++) { - u16 value; - memcpy(&value, buffer + count * sizeof(u16), sizeof(u16)); + uint16_t value; + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); /* MRC p14,0,r1,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); @@ -1233,10 +1345,10 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count } case 4: { - u32 instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00; + uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00; - /** \todo TODO: buffer cast to u32* causes alignment warnings */ - u32 *words = (u32*)buffer; + /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ + uint32_t *words = (uint32_t*)buffer; if (!arm11_config_memwrite_burst) { @@ -1259,14 +1371,14 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count /* r0 verification */ if (!arm11_config_memrw_no_increment) { - u32 r0; + uint32_t r0; /* MCR p14,0,R0,c0,c5,0 */ arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1); if (address + size * count != r0) { - LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count); + LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count)); if (arm11_config_memwrite_burst) LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); @@ -1284,7 +1396,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer) +int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer) { FNC_INFO; @@ -1301,7 +1413,7 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 * fallback code will read data from the target and calculate the CRC on the * host. */ -int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) +int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) { return ERROR_FAIL; } @@ -1368,14 +1480,14 @@ int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) // HACKHACKHACK - FIXME mode/state /* target algorithm support */ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, - int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, + int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) { arm11_common_t *arm11 = target->arch_info; // enum armv4_5_state core_state = arm11->core_state; // enum armv4_5_mode core_mode = arm11->core_mode; - u32 context[16]; - u32 cpsr; + uint32_t context[16]; + uint32_t cpsr; int exit_breakpoint_size = 0; int retval = ERROR_OK; LOG_DEBUG("Running algorithm"); @@ -1394,12 +1506,12 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t // Save regs for (size_t i = 0; i < 16; i++) { - context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32); - LOG_DEBUG("Save %zi: 0x%x",i,context[i]); + context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32); + LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]); } - cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32); - LOG_DEBUG("Save CPSR: 0x%x", cpsr); + cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32); + LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr); for (int i = 0; i < num_mem_params; i++) { @@ -1478,7 +1590,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point) { - LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x", + LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", buf_get_u32(arm11->reg_list[15].value, 0, 32)); retval = ERROR_TARGET_TIMEOUT; goto del_breakpoint; @@ -1518,12 +1630,12 @@ restore: // Restore context for (size_t i = 0; i < 16; i++) { - LOG_DEBUG("restoring register %s with value 0x%8.8x", + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", arm11->reg_list[i].name, context[i]); - arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]); + arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]); } - LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr); - arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr); + LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr); + arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr); // arm11->core_state = core_state; // arm11->core_mode = core_mode; @@ -1539,7 +1651,7 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp) arm11->target = target; - if (target->tap==NULL) + if (target->tap == NULL) return ERROR_FAIL; if (target->tap->ir_length != 5) @@ -1619,9 +1731,9 @@ int arm11_examine(struct target_s *target) arm11->free_brps = arm11->brp; arm11->free_wrps = arm11->wrp; - LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x", + LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "", arm11->device_id, - arm11->implementor, + (int)(arm11->implementor), arm11->didr); /* as a side-effect this reads DSCR and thus @@ -1631,7 +1743,7 @@ int arm11_examine(struct target_s *target) arm11_check_init(arm11, NULL); - target->type->examined = 1; + target_set_examined(target); return ERROR_OK; } @@ -1667,7 +1779,7 @@ int arm11_get_reg(reg_t *reg) } /** Change a value in the register cache */ -int arm11_set_reg(reg_t *reg, u8 *buf) +int arm11_set_reg(reg_t *reg, uint8_t *buf) { FNC_INFO; @@ -1729,7 +1841,7 @@ int arm11_build_reg_cache(target_t *target) r->name = rd->name; r->size = 32; - r->value = (u8 *)(arm11->reg_values + i); + r->value = (uint8_t *)(arm11->reg_values + i); r->dirty = 0; r->valid = 0; r->bitfield_desc = NULL; @@ -1802,6 +1914,7 @@ BOOL_WRAPPER(memwrite_burst, "memory write burst mode") BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers") BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") +BOOL_WRAPPER(hardware_step, "hardware single step") int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { @@ -1814,11 +1927,11 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, return ERROR_COMMAND_SYNTAX_ERROR; } - LOG_INFO("VCR 0x%08X", arm11_vcr); + LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr); return ERROR_OK; } -const u32 arm11_coproc_instruction_limits[] = +const uint32_t arm11_coproc_instruction_limits[] = { 15, /* coprocessor */ 7, /* opcode 1 */ @@ -1836,7 +1949,7 @@ arm11_common_t * arm11_find_target(const char * arg) jtag_tap_t * tap; target_t * t; - tap = jtag_TapByString(arg); + tap = jtag_tap_by_string(arg); if (!tap) return 0; @@ -1847,7 +1960,7 @@ arm11_common_t * arm11_find_target(const char * arg) continue; /* if (t->type == arm11_target) */ - if (0 == strcmp(t->type->name, "arm11")) + if (0 == strcmp(target_get_name(t), "arm11")) return t->arch_info; } @@ -1878,7 +1991,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar return ERROR_TARGET_NOT_HALTED; } - u32 values[6]; + uint32_t values[6]; for (size_t i = 0; i < (read ? 5 : 6); i++) { @@ -1886,14 +1999,15 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar if (values[i] > arm11_coproc_instruction_limits[i]) { - LOG_ERROR("Parameter %ld out of bounds (%d max). %s", - (long)(i + 2), arm11_coproc_instruction_limits[i], + LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s", + (long)(i + 2), + arm11_coproc_instruction_limits[i], read ? arm11_mrc_syntax : arm11_mcr_syntax); return -1; } } - u32 instr = 0xEE000010 | + uint32_t instr = 0xEE000010 | (values[0] << 8) | (values[1] << 21) | (values[2] << 16) | @@ -1907,20 +2021,24 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar if (read) { - u32 result; + uint32_t result; arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); - LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)", - values[0], values[1], values[2], values[3], values[4], result, result); + LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")", + (int)(values[0]), + (int)(values[1]), + (int)(values[2]), + (int)(values[3]), + (int)(values[4]), result, result); } else { arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); - LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d", - values[0], values[1], - values[5], - values[2], values[3], values[4]); + LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d", + (int)(values[0]), (int)(values[1]), + values[5], + (int)(values[2]), (int)(values[3]), (int)(values[4])); } arm11_run_instr_data_finish(arm11); @@ -1945,32 +2063,34 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) command_t * top_cmd = NULL; - RC_TOP( "arm11", "arm11 specific commands", + RC_TOP("arm11", "arm11 specific commands", - RC_TOP( "memwrite", "Control memory write transfer mode", + RC_TOP("memwrite", "Control memory write transfer mode", - RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", + RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", memwrite_burst) - RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)", + RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)", memwrite_error_fatal) - ) /* memwrite */ +) /* memwrite */ - RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)", + RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)", memrw_no_increment) - RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)", - step_irq_enable) +RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)", + step_irq_enable) +RC_FINAL_BOOL("hardware_step", "hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.", + hardware_step) - RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register", + RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register", arm11_handle_vcr) - RC_FINAL( "mrc", "Read Coprocessor register", + RC_FINAL("mrc", "Read Coprocessor register", arm11_handle_mrc) - RC_FINAL( "mcr", "Write Coprocessor register", + RC_FINAL("mcr", "Write Coprocessor register", arm11_handle_mcr) - ) /* arm11 */ +) /* arm11 */ return ERROR_OK; }