X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=30dbedb93975cbe2cc84a693617d160a5e5ad62e;hp=cb1af7bf1fb42ba99de8b0369f0bff643db5d1e9;hb=177bbd8891ae737ea7f8c0791a6236f72cedee40;hpb=b8b1353dd798d4aa811cdccc8eb2d6b41c1090d4 diff --git a/src/target/arm11.c b/src/target/arm11.c index cb1af7bf1f..30dbedb939 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -48,26 +48,6 @@ static bool arm11_config_hardware_step = false; enum arm11_regtype { - ARM11_REGISTER_CORE, - ARM11_REGISTER_CPSR, - - ARM11_REGISTER_FX, - ARM11_REGISTER_FPS, - - ARM11_REGISTER_FIQ, - ARM11_REGISTER_SVC, - ARM11_REGISTER_ABT, - ARM11_REGISTER_IRQ, - ARM11_REGISTER_UND, - ARM11_REGISTER_MON, - - ARM11_REGISTER_SPSR_FIQ, - ARM11_REGISTER_SPSR_SVC, - ARM11_REGISTER_SPSR_ABT, - ARM11_REGISTER_SPSR_IRQ, - ARM11_REGISTER_SPSR_UND, - ARM11_REGISTER_SPSR_MON, - /* debug regs */ ARM11_REGISTER_DSCR, ARM11_REGISTER_WDTR, @@ -86,25 +66,6 @@ struct arm11_reg_defs /* update arm11_regcache_ids when changing this */ static const struct arm11_reg_defs arm11_reg_defs[] = { - {"r0", 0, 0, ARM11_REGISTER_CORE}, - {"r1", 1, 1, ARM11_REGISTER_CORE}, - {"r2", 2, 2, ARM11_REGISTER_CORE}, - {"r3", 3, 3, ARM11_REGISTER_CORE}, - {"r4", 4, 4, ARM11_REGISTER_CORE}, - {"r5", 5, 5, ARM11_REGISTER_CORE}, - {"r6", 6, 6, ARM11_REGISTER_CORE}, - {"r7", 7, 7, ARM11_REGISTER_CORE}, - {"r8", 8, 8, ARM11_REGISTER_CORE}, - {"r9", 9, 9, ARM11_REGISTER_CORE}, - {"r10", 10, 10, ARM11_REGISTER_CORE}, - {"r11", 11, 11, ARM11_REGISTER_CORE}, - {"r12", 12, 12, ARM11_REGISTER_CORE}, - {"sp", 13, 13, ARM11_REGISTER_CORE}, - {"lr", 14, 14, ARM11_REGISTER_CORE}, - {"pc", 15, 15, ARM11_REGISTER_CORE}, - - {"cpsr", 0, 25, ARM11_REGISTER_CPSR}, - /* Debug Registers */ {"dscr", 0, -1, ARM11_REGISTER_DSCR}, {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, @@ -113,30 +74,6 @@ static const struct arm11_reg_defs arm11_reg_defs[] = enum arm11_regcache_ids { - ARM11_RC_R0, - ARM11_RC_RX = ARM11_RC_R0, - - ARM11_RC_R1, - ARM11_RC_R2, - ARM11_RC_R3, - ARM11_RC_R4, - ARM11_RC_R5, - ARM11_RC_R6, - ARM11_RC_R7, - ARM11_RC_R8, - ARM11_RC_R9, - ARM11_RC_R10, - ARM11_RC_R11, - ARM11_RC_R12, - ARM11_RC_R13, - ARM11_RC_SP = ARM11_RC_R13, - ARM11_RC_R14, - ARM11_RC_LR = ARM11_RC_R14, - ARM11_RC_R15, - ARM11_RC_PC = ARM11_RC_R15, - - ARM11_RC_CPSR, - ARM11_RC_DSCR, ARM11_RC_WDTR, ARM11_RC_RDTR, @@ -144,9 +81,6 @@ enum arm11_regcache_ids ARM11_RC_MAX, }; -/* GDB expects ARMs to give R0..R15, CPSR, and 7 FPA dummies */ -#define ARM11_GDB_REGISTER_COUNT 26 - static int arm11_on_enter_debug_state(struct arm11_common *arm11); static int arm11_step(struct target *target, int current, uint32_t address, int handle_breakpoints); @@ -155,9 +89,6 @@ static int arm11_build_reg_cache(struct target *target); static int arm11_set_reg(struct reg *reg, uint8_t *buf); static int arm11_get_reg(struct reg *reg); -static void arm11_record_register_history(struct arm11_common * arm11); -static void arm11_dump_reg_changes(struct arm11_common * arm11); - /** Check and if necessary take control of the system * @@ -226,12 +157,17 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) { int retval; + /* REVISIT entire cache should already be invalid !!! */ + register_cache_invalidate(arm11->arm.core_cache); + for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) { arm11->reg_list[i].valid = 1; arm11->reg_list[i].dirty = 0; } + /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ + /* Save DSCR */ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR))); @@ -257,10 +193,12 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) } - /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */ - /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs - ARM1136 seems to require this to issue ITR's as well */ - + /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE + * + * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", + * but not to issue ITRs. ARM1136 seems to require this to issue + * ITR's as well... + */ uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; /* this executes JTAG queue: */ @@ -300,23 +238,20 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) } #endif + /* Save registers. + * + * NOTE: ARM1136 TRM suggests saving just R0 here now, then + * CPSR and PC after the rDTR stuff. We do it all at once. + */ + retval = arm_dpm_read_current_registers(&arm11->dpm); + if (retval != ERROR_OK) + LOG_ERROR("DPM REG READ -- fail %d", retval); + retval = arm11_run_instr_data_prepare(arm11); if (retval != ERROR_OK) return retval; - /* save r0 - r14 */ - - /** \todo TODO: handle other mode registers */ - - for (size_t i = 0; i < 15; i++) - { - /* MCR p14,0,R?,c0,c5,0 */ - retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); - if (retval != ERROR_OK) - return retval; - } - - /* save rDTR */ + /* maybe save rDTR */ /* check rDTRfull in DSCR */ @@ -332,34 +267,9 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) arm11->reg_list[ARM11_RC_RDTR].valid = 0; } - /* save CPSR */ - - /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */ - retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR)); - if (retval != ERROR_OK) - return retval; - - /* save PC */ - - /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */ - retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC)); - if (retval != ERROR_OK) - return retval; - - /* adjust PC depending on ARM state */ - - if (R(CPSR) & ARM11_CPSR_J) /* Java state */ - { - arm11->reg_values[ARM11_RC_PC] -= 0; - } - else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */ - { - arm11->reg_values[ARM11_RC_PC] -= 4; - } - else /* ARM state */ - { - arm11->reg_values[ARM11_RC_PC] -= 8; - } + /* REVISIT Now that we've saved core state, there's may also + * be MMU and cache state to care about ... + */ if (arm11->simulate_reset_on_next_halt) { @@ -380,41 +290,9 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) if (retval != ERROR_OK) return retval; - arm11_dump_reg_changes(arm11); - return ERROR_OK; } -static void arm11_dump_reg_changes(struct arm11_common * arm11) -{ - - if (!(debug_level >= LOG_LVL_DEBUG)) - { - return; - } - - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (!arm11->reg_list[i].valid) - { - if (arm11->reg_history[i].valid) - LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value); - } - else - { - if (arm11->reg_history[i].valid) - { - if (arm11->reg_history[i].value != arm11->reg_values[i]) - LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); - } - else - { - LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); - } - } - } -} - /** Restore processor state * * This is called in preparation for the RESTART function. @@ -424,29 +302,16 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) { int retval; - retval = arm11_run_instr_data_prepare(arm11); - if (retval != ERROR_OK) - return retval; - - /** \todo TODO: handle other mode registers */ + /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */ - /* restore R1 - R14 */ - - for (unsigned i = 1; i < 15; i++) - { - if (!arm11->reg_list[ARM11_RC_RX + i].dirty) - continue; - - /* MRC p14,0,r?,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, - 0xee100e15 | (i << 12), R(RX + i)); - - // LOG_DEBUG("RESTORE R%u %08x", i, R(RX + i)); - } + /* NOTE: the ARM1136 TRM suggests restoring all registers + * except R0/PC/CPSR right now. Instead, we do them all + * at once, just a bit later on. + */ - retval = arm11_run_instr_data_finish(arm11); - if (retval != ERROR_OK) - return retval; + /* REVISIT once we start caring about MMU and cache state, + * address it here ... + */ /* spec says clear wDTR and rDTR; we assume they are clear as otherwise our programming would be sloppy */ @@ -469,50 +334,35 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) } } - retval = arm11_run_instr_data_prepare(arm11); - if (retval != ERROR_OK) - return retval; - - /* restore original wDTR */ - + /* maybe restore original wDTR */ if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) { + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; + /* MCR p14,0,R0,c0,c5,0 */ retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); if (retval != ERROR_OK) return retval; - } - - /* restore CPSR */ - - /* MSR CPSR,R0*/ - retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR)); - if (retval != ERROR_OK) - return retval; - - - /* restore PC */ - - /* MOV PC,R0 */ - retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC)); - if (retval != ERROR_OK) - return retval; + retval = arm11_run_instr_data_finish(arm11); + if (retval != ERROR_OK) + return retval; + } - /* restore R0 */ - - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0)); + /* restore CPSR, PC, and R0 ... after flushing any modified + * registers. + */ + retval = arm_dpm_write_dirty_registers(&arm11->dpm); - retval = arm11_run_instr_data_finish(arm11); - if (retval != ERROR_OK) - return retval; + register_cache_invalidate(arm11->arm.core_cache); /* restore DSCR */ arm11_write_DSCR(arm11, R(DSCR)); - /* restore rDTR */ + /* maybe restore rDTR */ if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) { @@ -532,24 +382,11 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } - arm11_record_register_history(arm11); + /* now processor is ready to RESTART */ return ERROR_OK; } -static void arm11_record_register_history(struct arm11_common *arm11) -{ - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - arm11->reg_history[i].value = arm11->reg_values[i]; - arm11->reg_history[i].valid = arm11->reg_list[i].valid; - - arm11->reg_list[i].valid = 0; - arm11->reg_list[i].dirty = 0; - } -} - - /* poll current target status */ static int arm11_poll(struct target *target) { @@ -595,14 +432,13 @@ static int arm11_poll(struct target *target) /* architecture specific status reply */ static int arm11_arch_state(struct target *target) { - struct arm11_common *arm11 = target_to_arm11(target); + int retval; - LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - R(CPSR), - R(PC)); + retval = armv4_5_arch_state(target); - return ERROR_OK; + /* REVISIT also display ARM11-specific MMU and cache status ... */ + + return retval; } /* target request support */ @@ -678,6 +514,19 @@ static int arm11_halt(struct target *target) return ERROR_OK; } +static uint32_t +arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) +{ + void *value = arm11->arm.core_cache->reg_list[15].value; + + if (!current) + buf_set_u32(value, 0, 32, address); + else + address = buf_get_u32(value, 0, 32); + + return address; +} + static int arm11_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { @@ -696,16 +545,18 @@ static int arm11_resume(struct target *target, int current, return ERROR_TARGET_NOT_HALTED; } - if (!current) - R(PC) = address; + address = arm11_nextpc(arm11, current, address); - LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); + LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : ""); /* clear breakpoints/watchpoints and VCR*/ arm11_sc7_clear_vbw(arm11); - /* Set up breakpoints */ if (!debug_execution) + target_free_all_working_areas(target); + + /* Set up breakpoints */ + if (handle_breakpoints) { /* check if one matches PC and step over it if necessary */ @@ -713,7 +564,7 @@ static int arm11_resume(struct target *target, int current, for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->address == R(PC)) + if (bp->address == address) { LOG_DEBUG("must step over %08" PRIx32 "", bp->address); arm11_step(target, 1, 0, 0); @@ -800,96 +651,6 @@ static int arm11_resume(struct target *target, int current, return ERROR_OK; } - -static int armv4_5_to_arm11(int reg) -{ - if (reg < 16) - return reg; - switch (reg) - { - case ARMV4_5_CPSR: - return ARM11_RC_CPSR; - case 16: - /* FIX!!! handle thumb better! */ - return ARM11_RC_CPSR; - default: - LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg); - exit(-1); - } -} - - -static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg) -{ - struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - reg=armv4_5_to_arm11(reg); - - return buf_get_u32(arm11->reg_list[reg].value, 0, 32); -} - -static void arm11_sim_set_reg(struct arm_sim_interface *sim, - int reg, uint32_t value) -{ - struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - reg=armv4_5_to_arm11(reg); - - buf_set_u32(arm11->reg_list[reg].value, 0, 32, value); -} - -static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, - int pos, int bits) -{ - struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits); -} - -static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim) -{ -// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - /* FIX!!!! we should implement thumb for arm11 */ - return ARMV4_5_STATE_ARM; -} - -static void arm11_sim_set_state(struct arm_sim_interface *sim, - enum armv4_5_state mode) -{ -// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - /* FIX!!!! we should implement thumb for arm11 */ - LOG_ERROR("Not implemented: %s", __func__); -} - - -static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim) -{ - //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; - - /* FIX!!!! we should implement something that returns the current mode here!!! */ - return ARMV4_5_MODE_USR; -} - -static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc) -{ - struct arm_sim_interface sim; - - sim.user_data=target->arch_info; - sim.get_reg=&arm11_sim_get_reg; - sim.set_reg=&arm11_sim_set_reg; - sim.get_reg_mode=&arm11_sim_get_reg; - sim.set_reg_mode=&arm11_sim_set_reg; - sim.get_cpsr=&arm11_sim_get_cpsr; - sim.get_mode=&arm11_sim_get_mode; - sim.get_state=&arm11_sim_get_state; - sim.set_state=&arm11_sim_set_state; - - return arm_simulate_step_core(target, dry_run_pc, &sim); - -} - static int arm11_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { @@ -904,33 +665,28 @@ static int arm11_step(struct target *target, int current, struct arm11_common *arm11 = target_to_arm11(target); - if (!current) - R(PC) = address; + address = arm11_nextpc(arm11, current, address); - LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); + LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : ""); /** \todo TODO: Thumb not supported here */ uint32_t next_instruction; - CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction)); + CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction)); /* skip over BKPT */ if ((next_instruction & 0xFFF00070) == 0xe1200070) { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; + address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping BKPT"); } /* skip over Wait for interrupt / Standby */ /* mcr 15, 0, r?, cr7, cr0, {4} */ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; + address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping WFI"); } /* ignore B to self */ @@ -958,24 +714,41 @@ static int arm11_step(struct target *target, int current, if (arm11_config_hardware_step) { - /* hardware single stepping be used if possible or is it better to - * always use the same code path? Hardware single stepping is not supported - * on all hardware + /* Hardware single stepping ("instruction address + * mismatch") is used if enabled. It's not quite + * exactly "run one instruction"; "branch to here" + * loops won't break, neither will some other cases, + * but it's probably the best default. + * + * Hardware single stepping isn't supported on v6 + * debug modules. ARM1176 and v7 can support it... + * + * FIXME Thumb stepping likely needs to use 0x03 + * or 0xc0 byte masks, not 0x0f. */ - brp[0].value = R(PC); - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); + brp[0].value = address; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (2 << 21); } else { - /* sets a breakpoint on the next PC(calculated by simulation), + /* Sets a breakpoint on the next PC, as calculated + * by instruction set simulation. + * + * REVISIT stepping Thumb on ARM1156 requires Thumb2 + * support from the simulator. */ uint32_t next_pc; int retval; - retval = arm11_simulate_step(target, &next_pc); + + retval = arm_simulate_step(target, &next_pc); if (retval != ERROR_OK) return retval; brp[0].value = next_pc; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (0 << 21); } CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); @@ -1117,31 +890,6 @@ static int arm11_soft_reset_halt(struct target *target) return ERROR_FAIL; } -/* target register access for gdb */ -static int arm11_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size) -{ - struct arm11_common *arm11 = target_to_arm11(target); - - *reg_list_size = ARM11_GDB_REGISTER_COUNT; - *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT); - - /* nine unused legacy FPA registers are expected by GDB */ - for (size_t i = 16; i < 24; i++) - (*reg_list)[i] = &arm_gdb_dummy_fp_reg; - (*reg_list)[24] = &arm_gdb_dummy_fps_reg; - - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (arm11_reg_defs[i].gdb_num == -1) - continue; - - (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i; - } - - return ERROR_OK; -} - /* target memory access * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of @@ -1179,8 +927,7 @@ static int arm11_read_memory_inner(struct target *target, switch (size) { case 1: - /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */ - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1200,7 +947,7 @@ static int arm11_read_memory_inner(struct target *target, case 2: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1242,13 +989,14 @@ static int arm11_read_memory(struct target *target, uint32_t address, uint32_t s } /* -* arm11_config_memrw_no_increment - in the future we may want to be able +* no_increment - in the future we may want to be able * to read/write a range of data to a "port". a "port" is an action on * read memory address for some peripheral. */ static int arm11_write_memory_inner(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, - bool arm11_config_memrw_no_increment) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer, + bool no_increment) { int retval; @@ -1284,7 +1032,7 @@ static int arm11_write_memory_inner(struct target *target, { case 1: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1296,7 +1044,9 @@ static int arm11_write_memory_inner(struct target *target, /* strb r1, [r0], #1 */ /* strb r1, [r0] */ retval = arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000); + !no_increment + ? 0xe4c01001 + : 0xe5c01000); if (retval != ERROR_OK) return retval; } @@ -1306,7 +1056,7 @@ static int arm11_write_memory_inner(struct target *target, case 2: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1321,7 +1071,9 @@ static int arm11_write_memory_inner(struct target *target, /* strh r1, [r0], #2 */ /* strh r1, [r0] */ retval = arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0); + !no_increment + ? 0xe0c010b2 + : 0xe1c010b0); if (retval != ERROR_OK) return retval; } @@ -1330,7 +1082,7 @@ static int arm11_write_memory_inner(struct target *target, } case 4: { - uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00; + uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ uint32_t *words = (uint32_t*)buffer; @@ -1357,7 +1109,7 @@ static int arm11_write_memory_inner(struct target *target, } /* r0 verification */ - if (!arm11_config_memrw_no_increment) + if (!no_increment) { uint32_t r0; @@ -1385,9 +1137,14 @@ static int arm11_write_memory_inner(struct target *target, } static int arm11_write_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - return arm11_write_memory_inner(target, address, size, count, buffer, false); + /* pointer increment matters only for multi-unit writes ... + * not e.g. to a "reset the chip" controller. + */ + return arm11_write_memory_inner(target, address, size, + count, buffer, count == 1); } /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ @@ -1462,175 +1219,12 @@ static int arm11_remove_watchpoint(struct target *target, return ERROR_FAIL; } -// HACKHACKHACK - FIXME mode/state -/* target algorithm support */ -static int arm11_run_algorithm(struct target *target, - int num_mem_params, struct mem_param *mem_params, - int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) -{ - struct arm11_common *arm11 = target_to_arm11(target); -// enum armv4_5_state core_state = arm11->core_state; -// enum armv4_5_mode core_mode = arm11->core_mode; - uint32_t context[16]; - uint32_t cpsr; - int exit_breakpoint_size = 0; - int retval = ERROR_OK; - LOG_DEBUG("Running algorithm"); - - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - // FIXME -// if (!is_arm_mode(arm11->core_mode)) -// return ERROR_FAIL; - - // Save regs - for (unsigned i = 0; i < 16; i++) - { - context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32); - LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]); - } - - cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32); - LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr); - - for (int i = 0; i < num_mem_params; i++) - { - target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); - } - - // Set register parameters - for (int i = 0; i < num_reg_params; i++) - { - struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; - } - - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - return ERROR_INVALID_ARGUMENTS; - } - arm11_set_reg(reg,reg_params[i].value); -// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val); - } - - exit_breakpoint_size = 4; - -/* arm11->core_state = arm11_algorithm_info->core_state; - if (arm11->core_state == ARMV4_5_STATE_ARM) - exit_breakpoint_size = 4; - else if (arm11->core_state == ARMV4_5_STATE_THUMB) - exit_breakpoint_size = 2; - else - { - LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); - exit(-1); - } -*/ - - -/* arm11 at this point only supports ARM not THUMB mode - however if this test needs to be reactivated the current state can be read back - from CPSR */ -#if 0 - if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY) - { - LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode); - buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode); - arm11->reg_list[ARM11_RC_CPSR].dirty = 1; - arm11->reg_list[ARM11_RC_CPSR].valid = 1; - } -#endif - - if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) - { - LOG_ERROR("can't add breakpoint to finish algorithm execution"); - retval = ERROR_TARGET_FAILURE; - goto restore; - } - - // no debug, otherwise breakpoint is not set - CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0)); - - CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms)); - - if (target->state != TARGET_HALTED) - { - CHECK_RETVAL(target_halt(target)); - - CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500)); - - retval = ERROR_TARGET_TIMEOUT; - - goto del_breakpoint; - } - - if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point) - { - LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", - buf_get_u32(arm11->reg_list[15].value, 0, 32)); - retval = ERROR_TARGET_TIMEOUT; - goto del_breakpoint; - } - - for (int i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); - } - - for (int i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { - struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - retval = ERROR_INVALID_ARGUMENTS; - goto del_breakpoint; - } - - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - retval = ERROR_INVALID_ARGUMENTS; - goto del_breakpoint; - } - - buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); - } - } - -del_breakpoint: - breakpoint_remove(target, exit_point); - -restore: - // Restore context - for (size_t i = 0; i < 16; i++) - { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", - arm11->reg_list[i].name, context[i]); - arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]); - } - LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr); - arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr); - -// arm11->core_state = core_state; -// arm11->core_mode = core_mode; - - return retval; -} +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value); +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, + uint32_t CRm, uint32_t value); static int arm11_target_create(struct target *target, Jim_Interp *interp) { @@ -1651,6 +1245,9 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp) armv4_5_init_arch_info(target, &arm11->arm); + arm11->arm.mrc = arm11_mrc; + arm11->arm.mcr = arm11_mcr; + arm11->target = target; arm11->jtag_info.tap = target->tap; @@ -1667,9 +1264,9 @@ static int arm11_init_target(struct command_context *cmd_ctx, { /* Initialize anything we can set up without talking to the target */ - /* FIXME Switch to use the standard build_reg_cache() not custom - * code. Do it from examine(), after we check whether we're - * an arm1176 and thus support the Secure Monitor mode. + /* REVISIT do we really want such a debug-registers-only cache? + * If we do, it should probably be handled purely by the DPM code, + * so it works identically on the v7a/v7r cores. */ return arm11_build_reg_cache(target); } @@ -1683,6 +1280,8 @@ static int arm11_examine(struct target *target) uint32_t didr, device_id; uint8_t implementor; + /* FIXME split into do-first-time and do-every-time logic ... */ + /* check IDCODE */ arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); @@ -1755,6 +1354,14 @@ static int arm11_examine(struct target *target) if (retval != ERROR_OK) return retval; + /* Build register cache "late", after target_init(), since we + * want to know if this core supports Secure Monitor mode. + */ + if (!target_was_examined(target)) { + arm11_dpm_init(arm11, didr); + retval = arm_dpm_setup(&arm11->dpm); + } + /* ETM on ARM11 still uses original scanchain 6 access mode */ if (arm11->arm.etm && !target_was_examined(target)) { *register_get_last_cache_p(&target->reg_cache) = @@ -1829,9 +1436,8 @@ static int arm11_build_reg_cache(struct target *target) arm11->reg_list = reg_list; - /* Build the process context cache */ - cache->name = "arm11 registers"; - cache->next = NULL; + /* build cache for some of the debug registers */ + cache->name = "arm11 debug registers"; cache->reg_list = reg_list; cache->num_regs = ARM11_REGCACHE_COUNT; @@ -1839,7 +1445,6 @@ static int arm11_build_reg_cache(struct target *target) (*cache_p) = cache; arm11->core_cache = cache; -// armv7m->process_context = cache; size_t i; @@ -1880,6 +1485,13 @@ static int arm11_build_reg_cache(struct target *target) return ERROR_OK; } +/* FIXME all these BOOL_WRAPPER things should be modifying + * per-instance state, not shared state; ditto the vector + * catch register support. Scan chains with multiple cores + * should be able to say "work with this core like this, + * that core like that". Example, ARM11 MPCore ... + */ + #define ARM11_BOOL_WRAPPER(name, print_name) \ COMMAND_HANDLER(arm11_handle_bool_##name) \ { \ @@ -1973,45 +1585,71 @@ static int arm11_mcr(struct target *target, int cpnum, return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } -static int arm11_register_commands(struct command_context *cmd_ctx) -{ - struct command *top_cmd, *mw_cmd; - - armv4_5_register_commands(cmd_ctx); - - top_cmd = register_command(cmd_ctx, NULL, "arm11", - NULL, COMMAND_ANY, NULL); - - /* "hardware_step" is only here to check if the default - * simulate + breakpoint implementation is broken. - * TEMPORARY! NOT DOCUMENTED! - */ - register_command(cmd_ctx, top_cmd, "hardware_step", - arm11_handle_bool_hardware_step, COMMAND_ANY, - "DEBUG ONLY - Hardware single stepping" - " (default: disabled)"); - - mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite", - NULL, COMMAND_ANY, NULL); - register_command(cmd_ctx, mw_cmd, "burst", - arm11_handle_bool_memwrite_burst, COMMAND_ANY, - "Enable/Disable non-standard but fast burst mode" - " (default: enabled)"); - register_command(cmd_ctx, mw_cmd, "error_fatal", - arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY, - "Terminate program if transfer error was found" - " (default: enabled)"); - - register_command(cmd_ctx, top_cmd, "step_irq_enable", - arm11_handle_bool_step_irq_enable, COMMAND_ANY, - "Enable interrupts while stepping" - " (default: disabled)"); - register_command(cmd_ctx, top_cmd, "vcr", - arm11_handle_vcr, COMMAND_ANY, - "Control (Interrupt) Vector Catch Register"); - - return etm_register_commands(cmd_ctx); -} +static const struct command_registration arm11_mw_command_handlers[] = { + { + .name = "burst", + .handler = &arm11_handle_bool_memwrite_burst, + .mode = COMMAND_ANY, + .help = "Enable/Disable non-standard but fast burst mode" + " (default: enabled)", + }, + { + .name = "error_fatal", + .handler = &arm11_handle_bool_memwrite_error_fatal, + .mode = COMMAND_ANY, + .help = "Terminate program if transfer error was found" + " (default: enabled)", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_any_command_handlers[] = { + { + /* "hardware_step" is only here to check if the default + * simulate + breakpoint implementation is broken. + * TEMPORARY! NOT DOCUMENTED! */ + .name = "hardware_step", + .handler = &arm11_handle_bool_hardware_step, + .mode = COMMAND_ANY, + .help = "DEBUG ONLY - Hardware single stepping" + " (default: disabled)", + .usage = "(enable|disable)", + }, + { + .name = "memwrite", + .mode = COMMAND_ANY, + .help = "memwrite command group", + .chain = arm11_mw_command_handlers, + }, + { + .name = "step_irq_enable", + .handler = &arm11_handle_bool_step_irq_enable, + .mode = COMMAND_ANY, + .help = "Enable interrupts while stepping" + " (default: disabled)", + }, + { + .name = "vcr", + .handler = &arm11_handle_vcr, + .mode = COMMAND_ANY, + .help = "Control (Interrupt) Vector Catch Register", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .chain = etm_command_handlers, + }, + { + .name = "arm11", + .mode = COMMAND_ANY, + .help = "ARM11 command group", + .chain = arm11_any_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM11xx targets. */ struct target_type arm11_target = { @@ -2030,7 +1668,7 @@ struct target_type arm11_target = { .deassert_reset = arm11_deassert_reset, .soft_reset_halt = arm11_soft_reset_halt, - .get_gdb_reg_list = arm11_get_gdb_reg_list, + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm11_read_memory, .write_memory = arm11_write_memory, @@ -2045,13 +1683,10 @@ struct target_type arm11_target = { .add_watchpoint = arm11_add_watchpoint, .remove_watchpoint = arm11_remove_watchpoint, - .run_algorithm = arm11_run_algorithm, + .run_algorithm = armv4_5_run_algorithm, - .register_commands = arm11_register_commands, + .commands = arm11_command_handlers, .target_create = arm11_target_create, .init_target = arm11_init_target, .examine = arm11_examine, - - .mrc = arm11_mrc, - .mcr = arm11_mcr, };