X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=30dbedb93975cbe2cc84a693617d160a5e5ad62e;hp=57dcd2f822b91f8bc5684e3bf0fb3e024fc0a8c7;hb=177bbd8891ae737ea7f8c0791a6236f72cedee40;hpb=2e779198535580515dfa9c8bfe1f3fe08abdb84b diff --git a/src/target/arm11.c b/src/target/arm11.c index 57dcd2f822..30dbedb939 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -2,7 +2,7 @@ * Copyright (C) 2008 digenius technology GmbH. * * Michael Bruck * * * - * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * * * * Copyright (C) 2008 Georg Acher * * * @@ -26,102 +26,28 @@ #include "config.h" #endif -#include "arm11.h" +#include "etm.h" +#include "breakpoints.h" +#include "arm11_dbgtap.h" +#include "arm_simulator.h" +#include "time_support.h" #include "target_type.h" +#include "algorithm.h" +#include "register.h" #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -#if 0 -#define FNC_INFO LOG_DEBUG("-") -#else -#define FNC_INFO -#endif - -#if 1 -#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0) -#else -#define FNC_INFO_NOTIMPLEMENTED -#endif - -static int arm11_on_enter_debug_state(arm11_common_t * arm11); - -bool arm11_config_memwrite_burst = true; -bool arm11_config_memwrite_error_fatal = true; -uint32_t arm11_vcr = 0; -bool arm11_config_memrw_no_increment = false; -bool arm11_config_step_irq_enable = false; - -#define ARM11_HANDLER(x) \ - .x = arm11_##x - -target_type_t arm11_target = -{ - .name = "arm11", - - ARM11_HANDLER(poll), - ARM11_HANDLER(arch_state), - - ARM11_HANDLER(target_request_data), - - ARM11_HANDLER(halt), - ARM11_HANDLER(resume), - ARM11_HANDLER(step), - - ARM11_HANDLER(assert_reset), - ARM11_HANDLER(deassert_reset), - ARM11_HANDLER(soft_reset_halt), - - ARM11_HANDLER(get_gdb_reg_list), - - ARM11_HANDLER(read_memory), - ARM11_HANDLER(write_memory), - - ARM11_HANDLER(bulk_write_memory), - - ARM11_HANDLER(checksum_memory), - - ARM11_HANDLER(add_breakpoint), - ARM11_HANDLER(remove_breakpoint), - ARM11_HANDLER(add_watchpoint), - ARM11_HANDLER(remove_watchpoint), - - ARM11_HANDLER(run_algorithm), - - ARM11_HANDLER(register_commands), - ARM11_HANDLER(target_create), - ARM11_HANDLER(init_target), - ARM11_HANDLER(examine), - ARM11_HANDLER(quit), -}; - -int arm11_regs_arch_type = -1; - +static bool arm11_config_memwrite_burst = true; +static bool arm11_config_memwrite_error_fatal = true; +static uint32_t arm11_vcr = 0; +static bool arm11_config_step_irq_enable = false; +static bool arm11_config_hardware_step = false; enum arm11_regtype { - ARM11_REGISTER_CORE, - ARM11_REGISTER_CPSR, - - ARM11_REGISTER_FX, - ARM11_REGISTER_FPS, - - ARM11_REGISTER_FIQ, - ARM11_REGISTER_SVC, - ARM11_REGISTER_ABT, - ARM11_REGISTER_IRQ, - ARM11_REGISTER_UND, - ARM11_REGISTER_MON, - - ARM11_REGISTER_SPSR_FIQ, - ARM11_REGISTER_SPSR_SVC, - ARM11_REGISTER_SPSR_ABT, - ARM11_REGISTER_SPSR_IRQ, - ARM11_REGISTER_SPSR_UND, - ARM11_REGISTER_SPSR_MON, - /* debug regs */ ARM11_REGISTER_DSCR, ARM11_REGISTER_WDTR, @@ -129,80 +55,17 @@ enum arm11_regtype }; -typedef struct arm11_reg_defs_s +struct arm11_reg_defs { char * name; uint32_t num; int gdb_num; enum arm11_regtype type; -} arm11_reg_defs_t; +}; /* update arm11_regcache_ids when changing this */ -static const arm11_reg_defs_t arm11_reg_defs[] = +static const struct arm11_reg_defs arm11_reg_defs[] = { - {"r0", 0, 0, ARM11_REGISTER_CORE}, - {"r1", 1, 1, ARM11_REGISTER_CORE}, - {"r2", 2, 2, ARM11_REGISTER_CORE}, - {"r3", 3, 3, ARM11_REGISTER_CORE}, - {"r4", 4, 4, ARM11_REGISTER_CORE}, - {"r5", 5, 5, ARM11_REGISTER_CORE}, - {"r6", 6, 6, ARM11_REGISTER_CORE}, - {"r7", 7, 7, ARM11_REGISTER_CORE}, - {"r8", 8, 8, ARM11_REGISTER_CORE}, - {"r9", 9, 9, ARM11_REGISTER_CORE}, - {"r10", 10, 10, ARM11_REGISTER_CORE}, - {"r11", 11, 11, ARM11_REGISTER_CORE}, - {"r12", 12, 12, ARM11_REGISTER_CORE}, - {"sp", 13, 13, ARM11_REGISTER_CORE}, - {"lr", 14, 14, ARM11_REGISTER_CORE}, - {"pc", 15, 15, ARM11_REGISTER_CORE}, - -#if ARM11_REGCACHE_FREGS - {"f0", 0, 16, ARM11_REGISTER_FX}, - {"f1", 1, 17, ARM11_REGISTER_FX}, - {"f2", 2, 18, ARM11_REGISTER_FX}, - {"f3", 3, 19, ARM11_REGISTER_FX}, - {"f4", 4, 20, ARM11_REGISTER_FX}, - {"f5", 5, 21, ARM11_REGISTER_FX}, - {"f6", 6, 22, ARM11_REGISTER_FX}, - {"f7", 7, 23, ARM11_REGISTER_FX}, - {"fps", 0, 24, ARM11_REGISTER_FPS}, -#endif - - {"cpsr", 0, 25, ARM11_REGISTER_CPSR}, - -#if ARM11_REGCACHE_MODEREGS - {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ}, - {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ}, - {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ}, - {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ}, - {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ}, - {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ}, - {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ}, - {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ}, - - {"r13_svc", 13, -1, ARM11_REGISTER_SVC}, - {"r14_svc", 14, -1, ARM11_REGISTER_SVC}, - {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC}, - - {"r13_abt", 13, -1, ARM11_REGISTER_ABT}, - {"r14_abt", 14, -1, ARM11_REGISTER_ABT}, - {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT}, - - {"r13_irq", 13, -1, ARM11_REGISTER_IRQ}, - {"r14_irq", 14, -1, ARM11_REGISTER_IRQ}, - {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ}, - - {"r13_und", 13, -1, ARM11_REGISTER_UND}, - {"r14_und", 14, -1, ARM11_REGISTER_UND}, - {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND}, - - /* ARM1176 only */ - {"r13_mon", 13, -1, ARM11_REGISTER_MON}, - {"r14_mon", 14, -1, ARM11_REGISTER_MON}, - {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON}, -#endif - /* Debug Registers */ {"dscr", 0, -1, ARM11_REGISTER_DSCR}, {"wdtr", 0, -1, ARM11_REGISTER_WDTR}, @@ -211,74 +74,6 @@ static const arm11_reg_defs_t arm11_reg_defs[] = enum arm11_regcache_ids { - ARM11_RC_R0, - ARM11_RC_RX = ARM11_RC_R0, - - ARM11_RC_R1, - ARM11_RC_R2, - ARM11_RC_R3, - ARM11_RC_R4, - ARM11_RC_R5, - ARM11_RC_R6, - ARM11_RC_R7, - ARM11_RC_R8, - ARM11_RC_R9, - ARM11_RC_R10, - ARM11_RC_R11, - ARM11_RC_R12, - ARM11_RC_R13, - ARM11_RC_SP = ARM11_RC_R13, - ARM11_RC_R14, - ARM11_RC_LR = ARM11_RC_R14, - ARM11_RC_R15, - ARM11_RC_PC = ARM11_RC_R15, - -#if ARM11_REGCACHE_FREGS - ARM11_RC_F0, - ARM11_RC_FX = ARM11_RC_F0, - ARM11_RC_F1, - ARM11_RC_F2, - ARM11_RC_F3, - ARM11_RC_F4, - ARM11_RC_F5, - ARM11_RC_F6, - ARM11_RC_F7, - ARM11_RC_FPS, -#endif - - ARM11_RC_CPSR, - -#if ARM11_REGCACHE_MODEREGS - ARM11_RC_R8_FIQ, - ARM11_RC_R9_FIQ, - ARM11_RC_R10_FIQ, - ARM11_RC_R11_FIQ, - ARM11_RC_R12_FIQ, - ARM11_RC_R13_FIQ, - ARM11_RC_R14_FIQ, - ARM11_RC_SPSR_FIQ, - - ARM11_RC_R13_SVC, - ARM11_RC_R14_SVC, - ARM11_RC_SPSR_SVC, - - ARM11_RC_R13_ABT, - ARM11_RC_R14_ABT, - ARM11_RC_SPSR_ABT, - - ARM11_RC_R13_IRQ, - ARM11_RC_R14_IRQ, - ARM11_RC_SPSR_IRQ, - - ARM11_RC_R13_UND, - ARM11_RC_R14_UND, - ARM11_RC_SPSR_UND, - - ARM11_RC_R13_MON, - ARM11_RC_R14_MON, - ARM11_RC_SPSR_MON, -#endif - ARM11_RC_DSCR, ARM11_RC_WDTR, ARM11_RC_RDTR, @@ -286,22 +81,13 @@ enum arm11_regcache_ids ARM11_RC_MAX, }; -#define ARM11_GDB_REGISTER_COUNT 26 - -uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - -reg_t arm11_gdb_dummy_fp_reg = -{ - "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 -}; - -uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; - -reg_t arm11_gdb_dummy_fps_reg = -{ - "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 -}; - +static int arm11_on_enter_debug_state(struct arm11_common *arm11); +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints); +/* helpers */ +static int arm11_build_reg_cache(struct target *target); +static int arm11_set_reg(struct reg *reg, uint8_t *buf); +static int arm11_get_reg(struct reg *reg); /** Check and if necessary take control of the system @@ -311,10 +97,8 @@ reg_t arm11_gdb_dummy_fps_reg = * available a pointer to a word holding the * DSCR can be passed. Otherwise use NULL. */ -int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) +static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr) { - FNC_INFO; - uint32_t dscr_local_tmp_copy; if (!dscr) @@ -369,16 +153,21 @@ int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) * or on other occasions that stop the processor. * */ -static int arm11_on_enter_debug_state(arm11_common_t * arm11) +static int arm11_on_enter_debug_state(struct arm11_common *arm11) { - FNC_INFO; + int retval; - for (size_t i = 0; i < asizeof(arm11->reg_values); i++) + /* REVISIT entire cache should already be invalid !!! */ + register_cache_invalidate(arm11->arm.core_cache); + + for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++) { arm11->reg_list[i].valid = 1; arm11->reg_list[i].dirty = 0; } + /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */ + /* Save DSCR */ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR))); @@ -390,13 +179,13 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } else { @@ -404,10 +193,12 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) } - /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */ - /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs - ARM1136 seems to require this to issue ITR's as well */ - + /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE + * + * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", + * but not to issue ITRs. ARM1136 seems to require this to issue + * ITR's as well... + */ uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE; /* this executes JTAG queue: */ @@ -447,56 +238,38 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) } #endif - arm11_run_instr_data_prepare(arm11); - - /* save r0 - r14 */ - - /** \todo TODO: handle other mode registers */ + /* Save registers. + * + * NOTE: ARM1136 TRM suggests saving just R0 here now, then + * CPSR and PC after the rDTR stuff. We do it all at once. + */ + retval = arm_dpm_read_current_registers(&arm11->dpm); + if (retval != ERROR_OK) + LOG_ERROR("DPM REG READ -- fail %d", retval); - for (size_t i = 0; i < 15; i++) - { - /* MCR p14,0,R?,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1); - } + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - /* save rDTR */ + /* maybe save rDTR */ /* check rDTRfull in DSCR */ if (R(DSCR) & ARM11_DSCR_RDTR_FULL) { /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); + retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR)); + if (retval != ERROR_OK) + return retval; } else { arm11->reg_list[ARM11_RC_RDTR].valid = 0; } - /* save CPSR */ - - /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR)); - - /* save PC */ - - /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */ - arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC)); - - /* adjust PC depending on ARM state */ - - if (R(CPSR) & ARM11_CPSR_J) /* Java state */ - { - arm11->reg_values[ARM11_RC_PC] -= 0; - } - else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */ - { - arm11->reg_values[ARM11_RC_PC] -= 4; - } - else /* ARM state */ - { - arm11->reg_values[ARM11_RC_PC] -= 8; - } + /* REVISIT Now that we've saved core state, there's may also + * be MMU and cache state to care about ... + */ if (arm11->simulate_reset_on_next_halt) { @@ -507,74 +280,38 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */ /* MCR p15,0,R0,c1,c0,0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0); + retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0); + if (retval != ERROR_OK) + return retval; } - arm11_run_instr_data_finish(arm11); - - arm11_dump_reg_changes(arm11); + retval = arm11_run_instr_data_finish(arm11); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -void arm11_dump_reg_changes(arm11_common_t * arm11) -{ - - if (!(debug_level >= LOG_LVL_DEBUG)) - { - return; - } - - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (!arm11->reg_list[i].valid) - { - if (arm11->reg_history[i].valid) - LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value); - } - else - { - if (arm11->reg_history[i].valid) - { - if (arm11->reg_history[i].value != arm11->reg_values[i]) - LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); - } - else - { - LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); - } - } - } -} - /** Restore processor state * * This is called in preparation for the RESTART function. * */ -int arm11_leave_debug_state(arm11_common_t * arm11) +static int arm11_leave_debug_state(struct arm11_common *arm11) { - FNC_INFO; - - arm11_run_instr_data_prepare(arm11); - - /** \todo TODO: handle other mode registers */ + int retval; - /* restore R1 - R14 */ + /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */ - for (size_t i = 1; i < 15; i++) - { - if (!arm11->reg_list[ARM11_RC_RX + i].dirty) - continue; - - /* MRC p14,0,r?,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i)); - - // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i)); - } + /* NOTE: the ARM1136 TRM suggests restoring all registers + * except R0/PC/CPSR right now. Instead, we do them all + * at once, just a bit later on. + */ - arm11_run_instr_data_finish(arm11); + /* REVISIT once we start caring about MMU and cache state, + * address it here ... + */ /* spec says clear wDTR and rDTR; we assume they are clear as otherwise our programming would be sloppy */ @@ -585,42 +322,47 @@ int arm11_leave_debug_state(arm11_common_t * arm11) if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) { + /* + The wDTR/rDTR two registers that are used to send/receive data to/from + the core in tandem with corresponding instruction codes that are + written into the core. The RDTR FULL/WDTR FULL flag indicates that the + registers hold data that was written by one side (CPU or JTAG) and not + read out by the other side. + */ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); + return ERROR_FAIL; } } - arm11_run_instr_data_prepare(arm11); - - /* restore original wDTR */ - + /* maybe restore original wDTR */ if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty) { - /* MCR p14,0,R0,c0,c5,0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); - } - - /* restore CPSR */ - - /* MSR CPSR,R0*/ - arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR)); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - /* restore PC */ - - /* MOV PC,R0 */ - arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC)); + /* MCR p14,0,R0,c0,c5,0 */ + retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR)); + if (retval != ERROR_OK) + return retval; - /* restore R0 */ + retval = arm11_run_instr_data_finish(arm11); + if (retval != ERROR_OK) + return retval; + } - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0)); + /* restore CPSR, PC, and R0 ... after flushing any modified + * registers. + */ + retval = arm_dpm_write_dirty_registers(&arm11->dpm); - arm11_run_instr_data_finish(arm11); + register_cache_invalidate(arm11->arm.core_cache); /* restore DSCR */ arm11_write_DSCR(arm11, R(DSCR)); - /* restore rDTR */ + /* maybe restore rDTR */ if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty) { @@ -628,7 +370,7 @@ int arm11_leave_debug_state(arm11_common_t * arm11) arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; uint8_t Ready = 0; /* ignored */ uint8_t Valid = 0; /* ignored */ @@ -637,37 +379,19 @@ int arm11_leave_debug_state(arm11_common_t * arm11) arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); } - arm11_record_register_history(arm11); + /* now processor is ready to RESTART */ return ERROR_OK; } -void arm11_record_register_history(arm11_common_t * arm11) -{ - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - arm11->reg_history[i].value = arm11->reg_values[i]; - arm11->reg_history[i].valid = arm11->reg_list[i].valid; - - arm11->reg_list[i].valid = 0; - arm11->reg_list[i].dirty = 0; - } -} - - /* poll current target status */ -int arm11_poll(struct target_s *target) +static int arm11_poll(struct target *target) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; - - if (arm11->trst_active) - return ERROR_OK; - + int retval; + struct arm11_common *arm11 = target_to_arm11(target); uint32_t dscr; CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); @@ -685,7 +409,9 @@ int arm11_poll(struct target_s *target) LOG_DEBUG("enter TARGET_HALTED"); target->state = TARGET_HALTED; target->debug_reason = arm11_get_DSCR_debug_reason(dscr); - arm11_on_enter_debug_state(arm11); + retval = arm11_on_enter_debug_state(arm11); + if (retval != ERROR_OK) + return retval; target_call_event_callbacks(target, old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); @@ -704,35 +430,33 @@ int arm11_poll(struct target_s *target) return ERROR_OK; } /* architecture specific status reply */ -int arm11_arch_state(struct target_s *target) +static int arm11_arch_state(struct target *target) { - arm11_common_t * arm11 = target->arch_info; + int retval; - LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - R(CPSR), - R(PC)); + retval = armv4_5_arch_state(target); - return ERROR_OK; + /* REVISIT also display ARM11-specific MMU and cache status ... */ + + return retval; } /* target request support */ -int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer) +static int arm11_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } /* target execution control */ -int arm11_halt(struct target_s *target) +static int arm11_halt(struct target *target) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name); + target_state_name(target)); if (target->state == TARGET_UNKNOWN) { @@ -745,24 +469,35 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } - if (arm11->trst_active) - { - arm11->halt_requested = true; - return ERROR_OK; - } - arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); uint32_t dscr; + int i = 0; while (1) { CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); if (dscr & ARM11_DSCR_CORE_HALTED) break; + + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; } arm11_on_enter_debug_state(arm11); @@ -779,17 +514,29 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } -int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static uint32_t +arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address) { - FNC_INFO; + void *value = arm11->arm.core_cache->reg_list[15].value; + + if (!current) + buf_set_u32(value, 0, 32, address); + else + address = buf_get_u32(value, 0, 32); + return address; +} + +static int arm11_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) +{ // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", // current, address, handle_breakpoints, debug_execution); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name); + target_state_name(target)); if (target->state != TARGET_HALTED) @@ -798,24 +545,26 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han return ERROR_TARGET_NOT_HALTED; } - if (!current) - R(PC) = address; + address = arm11_nextpc(arm11, current, address); - LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); + LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : ""); /* clear breakpoints/watchpoints and VCR*/ arm11_sc7_clear_vbw(arm11); - /* Set up breakpoints */ if (!debug_execution) + target_free_all_working_areas(target); + + /* Set up breakpoints */ + if (handle_breakpoints) { /* check if one matches PC and step over it if necessary */ - breakpoint_t * bp; + struct breakpoint * bp; for (bp = target->breakpoints; bp; bp = bp->next) { - if (bp->address == R(PC)) + if (bp->address == address) { LOG_DEBUG("must step over %08" PRIx32 "", bp->address); arm11_step(target, 1, 0, 0); @@ -825,11 +574,11 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han /* set all breakpoints */ - size_t brp_num = 0; + unsigned brp_num = 0; for (bp = target->breakpoints; bp; bp = bp->next) { - arm11_sc7_action_t brp[2]; + struct arm11_sc7_action brp[2]; brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0 + brp_num; @@ -838,9 +587,10 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han brp[1].address = ARM11_SC7_BCR0 + brp_num; brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21); - arm11_sc7_run(arm11, brp, asizeof(brp)); + arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)); - LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address); + LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num, + bp->address); brp_num++; } @@ -854,6 +604,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han CHECK_RETVAL(jtag_execute_queue()); + int i = 0; while (1) { uint32_t dscr; @@ -864,6 +615,22 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han if (dscr & ARM11_DSCR_CORE_RESTARTED) break; + + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; } if (!debug_execution) @@ -884,12 +651,11 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han return ERROR_OK; } -int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { - FNC_INFO; - LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name); + target_state_name(target)); if (target->state != TARGET_HALTED) { @@ -897,34 +663,30 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl return ERROR_TARGET_NOT_HALTED; } - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - if (!current) - R(PC) = address; + address = arm11_nextpc(arm11, current, address); + + LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : ""); - LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : ""); /** \todo TODO: Thumb not supported here */ uint32_t next_instruction; - CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction)); + CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction)); /* skip over BKPT */ if ((next_instruction & 0xFFF00070) == 0xe1200070) { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; + address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping BKPT"); } /* skip over Wait for interrupt / Standby */ /* mcr 15, 0, r?, cr7, cr0, {4} */ else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) { - R(PC) += 4; - arm11->reg_list[ARM11_RC_PC].valid = 1; - arm11->reg_list[ARM11_RC_PC].dirty = 0; + address = arm11_nextpc(arm11, 0, address + 4); LOG_DEBUG("Skipping WFI"); } /* ignore B to self */ @@ -943,16 +705,53 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl /* Set up breakpoint for stepping */ - arm11_sc7_action_t brp[2]; + struct arm11_sc7_action brp[2]; brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0; - brp[0].value = R(PC); brp[1].write = 1; brp[1].address = ARM11_SC7_BCR0; - brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21); - CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp))); + if (arm11_config_hardware_step) + { + /* Hardware single stepping ("instruction address + * mismatch") is used if enabled. It's not quite + * exactly "run one instruction"; "branch to here" + * loops won't break, neither will some other cases, + * but it's probably the best default. + * + * Hardware single stepping isn't supported on v6 + * debug modules. ARM1176 and v7 can support it... + * + * FIXME Thumb stepping likely needs to use 0x03 + * or 0xc0 byte masks, not 0x0f. + */ + brp[0].value = address; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (2 << 21); + } else + { + /* Sets a breakpoint on the next PC, as calculated + * by instruction set simulation. + * + * REVISIT stepping Thumb on ARM1156 requires Thumb2 + * support from the simulator. + */ + uint32_t next_pc; + int retval; + + retval = arm_simulate_step(target, &next_pc); + if (retval != ERROR_OK) + return retval; + + brp[0].value = next_pc; + brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) + | (0 << 14) | (0 << 16) | (0 << 20) + | (0 << 21); + } + + CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp))); /* resume */ @@ -969,10 +768,8 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl CHECK_RETVAL(jtag_execute_queue()); - /** \todo TODO: add a timeout */ - /* wait for halt */ - + int i = 0; while (1) { uint32_t dscr; @@ -984,6 +781,21 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) break; + + long long then = 0; + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + i++; } /* clear breakpoint */ @@ -1005,96 +817,93 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl return ERROR_OK; } -/* target reset control */ -int arm11_assert_reset(struct target_s *target) +static int arm11_assert_reset(struct target *target) { - FNC_INFO; - -#if 0 - /* assert reset lines */ - /* resets only the DBGTAP, not the ARM */ + int retval; + struct arm11_common *arm11 = target_to_arm11(target); - jtag_add_reset(1, 0); - jtag_add_sleep(5000); + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = true; -#endif + target->state = TARGET_UNKNOWN; + /* we would very much like to reset into the halted, state, + * but resetting and halting is second best... */ if (target->reset_halt) { CHECK_RETVAL(target_halt(target)); } - return ERROR_OK; -} - -int arm11_deassert_reset(struct target_s *target) -{ - FNC_INFO; - -#if 0 - LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name); + /* srst is funny. We can not do *anything* else while it's asserted + * and it has unkonwn side effects. Make sure no other code runs + * meanwhile. + * + * Code below assumes srst: + * + * - Causes power-on-reset (but of what parts of the system?). Bug + * in arm11? + * + * - Messes us TAP state without asserting trst. + * + * - There is another bug in the arm11 core. When you generate an access to + * external logic (for example ddr controller via AHB bus) and that block + * is not configured (perhaps it is still held in reset), that transaction + * will never complete. This will hang arm11 core but it will also hang + * JTAG controller. Nothing, short of srst assertion will bring it out of + * this. + * + * Mysteries: + * + * - What should the PC be after an srst reset when starting in the halted + * state? + */ - /* deassert reset lines */ + jtag_add_reset(0, 1); jtag_add_reset(0, 0); - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = false; + /* How long do we have to wait? */ + jtag_add_sleep(5000); - if (arm11->halt_requested) - return arm11_halt(target); -#endif + /* un-mess up TAP state */ + jtag_add_tlr(); + + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + { + return retval; + } return ERROR_OK; } -int arm11_soft_reset_halt(struct target_s *target) +static int arm11_deassert_reset(struct target *target) { - FNC_INFO_NOTIMPLEMENTED; - return ERROR_OK; } -/* target register access for gdb */ -int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size) +static int arm11_soft_reset_halt(struct target *target) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; - - *reg_list_size = ARM11_GDB_REGISTER_COUNT; - *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT); - - for (size_t i = 16; i < 24; i++) - { - (*reg_list)[i] = &arm11_gdb_dummy_fp_reg; - } - - (*reg_list)[24] = &arm11_gdb_dummy_fps_reg; - - for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) - { - if (arm11_reg_defs[i].gdb_num == -1) - continue; - - (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i; - } + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } /* target memory access * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of + * + * arm11_config_memrw_no_increment - in the future we may want to be able + * to read/write a range of data to a "port". a "port" is an action on + * read memory address for some peripheral. */ -int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_read_memory_inner(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, + bool arm11_config_memrw_no_increment) { /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ - - FNC_INFO; + int retval; if (target->state != TARGET_HALTED) { @@ -1104,18 +913,21 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - arm11_run_instr_data_prepare(arm11); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + if (retval != ERROR_OK) + return retval; switch (size) { case 1: - /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */ - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1135,7 +947,7 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, case 2: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { @@ -1149,7 +961,7 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); uint16_t svalue = res; - memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t)); + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); } break; @@ -1168,14 +980,25 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, } } - arm11_run_instr_data_finish(arm11); + return arm11_run_instr_data_finish(arm11); +} - return ERROR_OK; +static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +{ + return arm11_read_memory_inner(target, address, size, count, buffer, false); } -int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +/* +* no_increment - in the future we may want to be able +* to read/write a range of data to a "port". a "port" is an action on +* read memory address for some peripheral. +*/ +static int arm11_write_memory_inner(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer, + bool no_increment) { - FNC_INFO; + int retval; if (target->state != TARGET_HALTED) { @@ -1185,28 +1008,47 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - arm11_run_instr_data_prepare(arm11); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + if (retval != ERROR_OK) + return retval; + + /* burst writes are not used for single words as those may well be + * reset init script writes. + * + * The other advantage is that as burst writes are default, we'll + * now exercise both burst and non-burst code paths with the + * default settings, increasing code coverage. + */ + bool burst = arm11_config_memwrite_burst && (count > 1); switch (size) { case 1: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { /* MRC p14,0,r1,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); + if (retval != ERROR_OK) + return retval; /* strb r1, [r0], #1 */ /* strb r1, [r0] */ - arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000); + retval = arm11_run_instr_no_data1(arm11, + !no_increment + ? 0xe4c01001 + : 0xe5c01000); + if (retval != ERROR_OK) + return retval; } break; @@ -1214,81 +1056,101 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, case 2: { - arm11->reg_list[ARM11_RC_R1].dirty = 1; + arm11->arm.core_cache->reg_list[1].dirty = true; for (size_t i = 0; i < count; i++) { uint16_t value; - memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t)); + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); /* MRC p14,0,r1,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); + if (retval != ERROR_OK) + return retval; /* strh r1, [r0], #2 */ /* strh r1, [r0] */ - arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0); + retval = arm11_run_instr_no_data1(arm11, + !no_increment + ? 0xe0c010b2 + : 0xe1c010b0); + if (retval != ERROR_OK) + return retval; } break; } case 4: { - uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00; + uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ uint32_t *words = (uint32_t*)buffer; - if (!arm11_config_memwrite_burst) + if (!burst) { /* STC p14,c5,[R0],#4 */ /* STC p14,c5,[R0]*/ - arm11_run_instr_data_to_core(arm11, instr, words, count); + retval = arm11_run_instr_data_to_core(arm11, instr, words, count); + if (retval != ERROR_OK) + return retval; } else { /* STC p14,c5,[R0],#4 */ /* STC p14,c5,[R0]*/ - arm11_run_instr_data_to_core_noack(arm11, instr, words, count); + retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count); + if (retval != ERROR_OK) + return retval; } break; } } -#if 1 /* r0 verification */ - if (!arm11_config_memrw_no_increment) + if (!no_increment) { uint32_t r0; /* MCR p14,0,R0,c0,c5,0 */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1); + retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1); + if (retval != ERROR_OK) + return retval; if (address + size * count != r0) { - LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count)); + LOG_ERROR("Data transfer failed. Expected end " + "address 0x%08x, got 0x%08x", + (unsigned) (address + size * count), + (unsigned) r0); - if (arm11_config_memwrite_burst) + if (burst) LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); if (arm11_config_memwrite_error_fatal) return ERROR_FAIL; } } -#endif - arm11_run_instr_data_finish(arm11); - - return ERROR_OK; + return arm11_run_instr_data_finish(arm11); } +static int arm11_write_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ + /* pointer increment matters only for multi-unit writes ... + * not e.g. to a "reset the chip" controller. + */ + return arm11_write_memory_inner(target, address, size, + count, buffer, count == 1); +} /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int arm11_bulk_write_memory(struct target *target, + uint32_t address, uint32_t count, uint8_t *buffer) { - FNC_INFO; - if (target->state != TARGET_HALTED) { LOG_WARNING("target was not halted"); @@ -1298,23 +1160,13 @@ int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t return arm11_write_memory(target, address, 4, count, buffer); } -/* here we have nothing target specific to contribute, so we fail and then the - * fallback code will read data from the target and calculate the CRC on the - * host. - */ -int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) -{ - return ERROR_FAIL; -} - /* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ -int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); #if 0 if (breakpoint->type == BKPT_SOFT) @@ -1341,204 +1193,42 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_remove_breakpoint(struct target *target, + struct breakpoint *breakpoint) { - FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); arm11->free_brps++; return ERROR_OK; } -int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_add_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } -int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_remove_watchpoint(struct target *target, + struct watchpoint *watchpoint) { - FNC_INFO_NOTIMPLEMENTED; + LOG_WARNING("Not implemented: %s", __func__); - return ERROR_OK; + return ERROR_FAIL; } -// HACKHACKHACK - FIXME mode/state -/* target algorithm support */ -int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, - int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) -{ - arm11_common_t *arm11 = target->arch_info; -// enum armv4_5_state core_state = arm11->core_state; -// enum armv4_5_mode core_mode = arm11->core_mode; - uint32_t context[16]; - uint32_t cpsr; - int exit_breakpoint_size = 0; - int retval = ERROR_OK; - LOG_DEBUG("Running algorithm"); - - - if (target->state != TARGET_HALTED) - { - LOG_WARNING("target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - // FIXME -// if (armv4_5_mode_to_number(arm11->core_mode)==-1) -// return ERROR_FAIL; - - // Save regs - for (size_t i = 0; i < 16; i++) - { - context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32); - LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]); - } - - cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32); - LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr); - - for (int i = 0; i < num_mem_params; i++) - { - target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); - } - - // Set register parameters - for (int i = 0; i < num_reg_params; i++) - { - reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); - } - - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); - } - arm11_set_reg(reg,reg_params[i].value); -// printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val); - } - - exit_breakpoint_size = 4; +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value); +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, + uint32_t CRm, uint32_t value); -/* arm11->core_state = arm11_algorithm_info->core_state; - if (arm11->core_state == ARMV4_5_STATE_ARM) - exit_breakpoint_size = 4; - else if (arm11->core_state == ARMV4_5_STATE_THUMB) - exit_breakpoint_size = 2; - else - { - LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state"); - exit(-1); - } -*/ - - -/* arm11 at this point only supports ARM not THUMB mode - however if this test needs to be reactivated the current state can be read back - from CPSR */ -#if 0 - if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY) - { - LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode); - buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode); - arm11->reg_list[ARM11_RC_CPSR].dirty = 1; - arm11->reg_list[ARM11_RC_CPSR].valid = 1; - } -#endif - - if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) - { - LOG_ERROR("can't add breakpoint to finish algorithm execution"); - retval = ERROR_TARGET_FAILURE; - goto restore; - } - - // no debug, otherwise breakpoint is not set - CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0)); - - CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms)); - - if (target->state != TARGET_HALTED) - { - CHECK_RETVAL(target_halt(target)); - - CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500)); - - retval = ERROR_TARGET_TIMEOUT; - - goto del_breakpoint; - } - - if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point) - { - LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", - buf_get_u32(arm11->reg_list[15].value, 0, 32)); - retval = ERROR_TARGET_TIMEOUT; - goto del_breakpoint; - } - - for (int i = 0; i < num_mem_params; i++) - { - if (mem_params[i].direction != PARAM_OUT) - target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value); - } - - for (int i = 0; i < num_reg_params; i++) - { - if (reg_params[i].direction != PARAM_OUT) - { - reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); - if (!reg) - { - LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); - exit(-1); - } - - if (reg->size != reg_params[i].size) - { - LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name); - exit(-1); - } - - buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32)); - } - } - -del_breakpoint: - breakpoint_remove(target, exit_point); - -restore: - // Restore context - for (size_t i = 0; i < 16; i++) - { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", - arm11->reg_list[i].name, context[i]); - arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]); - } - LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr); - arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr); - -// arm11->core_state = core_state; -// arm11->core_mode = core_mode; - - return retval; -} - -int arm11_target_create(struct target_s *target, Jim_Interp *interp) +static int arm11_target_create(struct target *target, Jim_Interp *interp) { - FNC_INFO; - - NEW(arm11_common_t, arm11, 1); - - arm11->target = target; + struct arm11_common *arm11; if (target->tap == NULL) return ERROR_FAIL; @@ -1549,31 +1239,56 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_COMMAND_SYNTAX_ERROR; } - target->arch_info = arm11; + arm11 = calloc(1, sizeof *arm11); + if (!arm11) + return ERROR_FAIL; + + armv4_5_init_arch_info(target, &arm11->arm); + + arm11->arm.mrc = arm11_mrc; + arm11->arm.mcr = arm11_mcr; + + arm11->target = target; + + arm11->jtag_info.tap = target->tap; + arm11->jtag_info.scann_size = 5; + arm11->jtag_info.scann_instr = ARM11_SCAN_N; + /* cur_scan_chain == 0 */ + arm11->jtag_info.intest_instr = ARM11_INTEST; return ERROR_OK; } -int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm11_init_target(struct command_context *cmd_ctx, + struct target *target) { /* Initialize anything we can set up without talking to the target */ + + /* REVISIT do we really want such a debug-registers-only cache? + * If we do, it should probably be handled purely by the DPM code, + * so it works identically on the v7a/v7r cores. + */ return arm11_build_reg_cache(target); } /* talk to the target and set things up */ -int arm11_examine(struct target_s *target) +static int arm11_examine(struct target *target) { - FNC_INFO; + int retval; + char *type; + struct arm11_common *arm11 = target_to_arm11(target); + uint32_t didr, device_id; + uint8_t implementor; - arm11_common_t * arm11 = target->arch_info; + /* FIXME split into do-first-time and do-every-time logic ... */ /* check IDCODE */ arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); - scan_field_t idcode_field; + struct scan_field idcode_field; - arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field); + arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field); arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE); @@ -1583,73 +1298,88 @@ int arm11_examine(struct target_s *target) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain0_fields[2]; + struct scan_field chain0_fields[2]; - arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); - arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); + arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0); + arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1); - arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); - switch (arm11->device_id & 0x0FFFF000) + switch (device_id & 0x0FFFF000) { - case 0x07B36000: LOG_INFO("found ARM1136"); break; - case 0x07B56000: LOG_INFO("found ARM1156"); break; - case 0x07B76000: LOG_INFO("found ARM1176"); break; + case 0x07B36000: + type = "ARM1136"; + break; + case 0x07B56000: + type = "ARM1156"; + break; + case 0x07B76000: + arm11->arm.core_type = ARM_MODE_MON; + type = "ARM1176"; + break; default: - { LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****"); return ERROR_FAIL; } - } - - arm11->debug_version = (arm11->didr >> 16) & 0x0F; + LOG_INFO("found %s", type); - if (arm11->debug_version != ARM11_DEBUG_V6 && - arm11->debug_version != ARM11_DEBUG_V61) - { - LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported."); + /* unlikely this could ever fail, but ... */ + switch ((didr >> 16) & 0x0F) { + case ARM11_DEBUG_V6: + case ARM11_DEBUG_V61: /* supports security extensions */ + break; + default: + LOG_ERROR("Only ARM v6 and v6.1 debug supported."); return ERROR_FAIL; } - arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1; - arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1; + arm11->brp = ((didr >> 24) & 0x0F) + 1; + arm11->wrp = ((didr >> 28) & 0x0F) + 1; /** \todo TODO: reserve one brp slot if we allow breakpoints during step */ arm11->free_brps = arm11->brp; arm11->free_wrps = arm11->wrp; - LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "", - arm11->device_id, - (int)(arm11->implementor), - arm11->didr); + LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32, + device_id, implementor, didr); /* as a side-effect this reads DSCR and thus * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag * as suggested by the spec. */ - arm11_check_init(arm11, NULL); + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; - target_set_examined(target); + /* Build register cache "late", after target_init(), since we + * want to know if this core supports Secure Monitor mode. + */ + if (!target_was_examined(target)) { + arm11_dpm_init(arm11, didr); + retval = arm_dpm_setup(&arm11->dpm); + } - return ERROR_OK; -} + /* ETM on ARM11 still uses original scanchain 6 access mode */ + if (arm11->arm.etm && !target_was_examined(target)) { + *register_get_last_cache_p(&target->reg_cache) = + etm_build_reg_cache(target, &arm11->jtag_info, + arm11->arm.etm); + retval = etm_setup(target); + } -int arm11_quit(void) -{ - FNC_INFO_NOTIMPLEMENTED; + target_set_examined(target); return ERROR_OK; } + /** Load a register that is marked !valid in the register cache */ -int arm11_get_reg(reg_t *reg) +static int arm11_get_reg(struct reg *reg) { - FNC_INFO; - - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; + struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target; if (target->state != TARGET_HALTED) { @@ -1660,82 +1390,92 @@ int arm11_get_reg(reg_t *reg) /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */ #if 0 - arm11_common_t *arm11 = target->arch_info; - const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; + struct arm11_common *arm11 = target_to_arm11(target); + const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; #endif return ERROR_OK; } /** Change a value in the register cache */ -int arm11_set_reg(reg_t *reg, uint8_t *buf) +static int arm11_set_reg(struct reg *reg, uint8_t *buf) { - FNC_INFO; - - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; - arm11_common_t *arm11 = target->arch_info; -// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; + struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target; + struct arm11_common *arm11 = target_to_arm11(target); +// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; - arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); + arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); reg->valid = 1; reg->dirty = 1; return ERROR_OK; } -int arm11_build_reg_cache(target_t *target) -{ - arm11_common_t *arm11 = target->arch_info; - - NEW(reg_cache_t, cache, 1); - NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT); - NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT); - - if (arm11_regs_arch_type == -1) - arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg); +static const struct reg_arch_type arm11_reg_type = { + .get = arm11_get_reg, + .set = arm11_set_reg, +}; - register_init_dummy(&arm11_gdb_dummy_fp_reg); - register_init_dummy(&arm11_gdb_dummy_fps_reg); +static int arm11_build_reg_cache(struct target *target) +{ + struct arm11_common *arm11 = target_to_arm11(target); + struct reg_cache *cache; + struct reg *reg_list; + struct arm11_reg_state *arm11_reg_states; + + cache = calloc(1, sizeof *cache); + reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list); + arm11_reg_states = calloc(ARM11_REGCACHE_COUNT, + sizeof *arm11_reg_states); + if (!cache || !reg_list || !arm11_reg_states) { + free(cache); + free(reg_list); + free(arm11_reg_states); + return ERROR_FAIL; + } arm11->reg_list = reg_list; - /* Build the process context cache */ - cache->name = "arm11 registers"; - cache->next = NULL; + /* build cache for some of the debug registers */ + cache->name = "arm11 debug registers"; cache->reg_list = reg_list; cache->num_regs = ARM11_REGCACHE_COUNT; - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); (*cache_p) = cache; arm11->core_cache = cache; -// armv7m->process_context = cache; size_t i; /* Not very elegant assertion */ - if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) || - ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || + if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) || + ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) || ARM11_REGCACHE_COUNT != ARM11_RC_MAX) { - LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); + LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)", + ARM11_REGCACHE_COUNT, + (unsigned) ARRAY_SIZE(arm11->reg_values), + (unsigned) ARRAY_SIZE(arm11_reg_defs), + ARM11_RC_MAX); + /* FIXME minimally, use a build_bug_on(X) mechanism; + * runtime exit() here is bad! + */ exit(-1); } for (i = 0; i < ARM11_REGCACHE_COUNT; i++) { - reg_t * r = reg_list + i; - const arm11_reg_defs_t * rd = arm11_reg_defs + i; - arm11_reg_state_t * rs = arm11_reg_states + i; + struct reg * r = reg_list + i; + const struct arm11_reg_defs * rd = arm11_reg_defs + i; + struct arm11_reg_state * rs = arm11_reg_states + i; r->name = rd->name; r->size = 32; r->value = (uint8_t *)(arm11->reg_values + i); r->dirty = 0; r->valid = 0; - r->bitfield_desc = NULL; - r->num_bitfields = 0; - r->arch_type = arm11_regs_arch_type; + r->type = &arm11_reg_type; r->arch_info = rs; rs->def_index = i; @@ -1745,73 +1485,34 @@ int arm11_build_reg_cache(target_t *target) return ERROR_OK; } -int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) -{ - if (argc == 0) - { - LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled"); - return ERROR_OK; - } - - if (argc != 1) - return ERROR_COMMAND_SYNTAX_ERROR; - - switch (args[0][0]) - { - case '0': /* 0 */ - case 'f': /* false */ - case 'F': - case 'd': /* disable */ - case 'D': - *var = false; - break; - - case '1': /* 1 */ - case 't': /* true */ - case 'T': - case 'e': /* enable */ - case 'E': - *var = true; - break; - } - - LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name); - - return ERROR_OK; -} - -#define BOOL_WRAPPER(name, print_name) \ -int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \ -{ \ - return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \ -} - -#define RC_TOP(name, descr, more) \ -{ \ - command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \ - command_t * top_cmd = new_cmd; \ - more \ -} - -#define RC_FINAL(name, descr, handler) \ - register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr); +/* FIXME all these BOOL_WRAPPER things should be modifying + * per-instance state, not shared state; ditto the vector + * catch register support. Scan chains with multiple cores + * should be able to say "work with this core like this, + * that core like that". Example, ARM11 MPCore ... + */ -#define RC_FINAL_BOOL(name, descr, var) \ - register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr); +#define ARM11_BOOL_WRAPPER(name, print_name) \ + COMMAND_HANDLER(arm11_handle_bool_##name) \ + { \ + return CALL_COMMAND_HANDLER(handle_command_parse_bool, \ + &arm11_config_##name, print_name); \ + } -BOOL_WRAPPER(memwrite_burst, "memory write burst mode") -BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") -BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers") -BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") +ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode") +ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") +ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") +ARM11_BOOL_WRAPPER(hardware_step, "hardware single step") -int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm11_handle_vcr) { - if (argc == 1) - { - arm11_vcr = strtoul(args[0], NULL, 0); - } - else if (argc != 0) - { + switch (CMD_ARGC) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr); + break; + default: return ERROR_COMMAND_SYNTAX_ERROR; } @@ -1819,7 +1520,7 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, return ERROR_OK; } -const uint32_t arm11_coproc_instruction_limits[] = +static const uint32_t arm11_coproc_instruction_limits[] = { 15, /* coprocessor */ 7, /* opcode 1 */ @@ -1829,154 +1530,163 @@ const uint32_t arm11_coproc_instruction_limits[] = 0xFFFFFFFF, /* value */ }; -const char arm11_mrc_syntax[] = "Syntax: mrc . All parameters are numbers only."; -const char arm11_mcr_syntax[] = "Syntax: mcr <32bit value to write>. All parameters are numbers only."; - -arm11_common_t * arm11_find_target(const char * arg) -{ - jtag_tap_t * tap; - target_t * t; - - tap = jtag_tap_by_string(arg); - - if (!tap) - return 0; - - for (t = all_targets; t; t = t->next) - { - if (t->tap != tap) - continue; - - /* if (t->type == arm11_target) */ - if (0 == strcmp(target_get_name(t), "arm11")) - return t->arch_info; - } - - return 0; -} - -int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read) +static int arm11_mrc_inner(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value, bool read) { - if (argc != (read ? 6 : 7)) - { - LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax); - return -1; - } - - arm11_common_t * arm11 = arm11_find_target(args[0]); + int retval; + struct arm11_common *arm11 = target_to_arm11(target); - if (!arm11) - { - LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s", - read ? arm11_mrc_syntax : arm11_mcr_syntax); - - return -1; - } - - if (arm11->target->state != TARGET_HALTED) - { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - uint32_t values[6]; - - for (size_t i = 0; i < (read ? 5 : 6); i++) + if (target->state != TARGET_HALTED) { - values[i] = strtoul(args[i + 1], NULL, 0); - - if (values[i] > arm11_coproc_instruction_limits[i]) - { - LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s", - (long)(i + 2), - arm11_coproc_instruction_limits[i], - read ? arm11_mrc_syntax : arm11_mcr_syntax); - return -1; - } + LOG_ERROR("Target not halted"); + return ERROR_FAIL; } uint32_t instr = 0xEE000010 | - (values[0] << 8) | - (values[1] << 21) | - (values[2] << 16) | - (values[3] << 0) | - (values[4] << 5); + (cpnum << 8) | + (op1 << 21) | + (CRn << 16) | + (CRm << 0) | + (op2 << 5); if (read) instr |= 0x00100000; - arm11_run_instr_data_prepare(arm11); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; if (read) { - uint32_t result; - arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); - - LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")", - (int)(values[0]), - (int)(values[1]), - (int)(values[2]), - (int)(values[3]), - (int)(values[4]), result, result); + retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value); + if (retval != ERROR_OK) + return retval; } else { - arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); - - LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d", - (int)(values[0]), (int)(values[1]), - values[5], - (int)(values[2]), (int)(values[3]), (int)(values[4])); + retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value); + if (retval != ERROR_OK) + return retval; } - arm11_run_instr_data_finish(arm11); - - - return ERROR_OK; + return arm11_run_instr_data_finish(arm11); } -int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true); } -int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } -int arm11_register_commands(struct command_context_s *cmd_ctx) -{ - FNC_INFO; +static const struct command_registration arm11_mw_command_handlers[] = { + { + .name = "burst", + .handler = &arm11_handle_bool_memwrite_burst, + .mode = COMMAND_ANY, + .help = "Enable/Disable non-standard but fast burst mode" + " (default: enabled)", + }, + { + .name = "error_fatal", + .handler = &arm11_handle_bool_memwrite_error_fatal, + .mode = COMMAND_ANY, + .help = "Terminate program if transfer error was found" + " (default: enabled)", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_any_command_handlers[] = { + { + /* "hardware_step" is only here to check if the default + * simulate + breakpoint implementation is broken. + * TEMPORARY! NOT DOCUMENTED! */ + .name = "hardware_step", + .handler = &arm11_handle_bool_hardware_step, + .mode = COMMAND_ANY, + .help = "DEBUG ONLY - Hardware single stepping" + " (default: disabled)", + .usage = "(enable|disable)", + }, + { + .name = "memwrite", + .mode = COMMAND_ANY, + .help = "memwrite command group", + .chain = arm11_mw_command_handlers, + }, + { + .name = "step_irq_enable", + .handler = &arm11_handle_bool_step_irq_enable, + .mode = COMMAND_ANY, + .help = "Enable interrupts while stepping" + " (default: disabled)", + }, + { + .name = "vcr", + .handler = &arm11_handle_vcr, + .mode = COMMAND_ANY, + .help = "Control (Interrupt) Vector Catch Register", + }, + COMMAND_REGISTRATION_DONE +}; +static const struct command_registration arm11_command_handlers[] = { + { + .chain = arm_command_handlers, + }, + { + .chain = etm_command_handlers, + }, + { + .name = "arm11", + .mode = COMMAND_ANY, + .help = "ARM11 command group", + .chain = arm11_any_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; - command_t * top_cmd = NULL; +/** Holds methods for ARM11xx targets. */ +struct target_type arm11_target = { + .name = "arm11", - RC_TOP("arm11", "arm11 specific commands", + .poll = arm11_poll, + .arch_state = arm11_arch_state, - RC_TOP("memwrite", "Control memory write transfer mode", + .target_request_data = arm11_target_request_data, - RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)", - memwrite_burst) + .halt = arm11_halt, + .resume = arm11_resume, + .step = arm11_step, - RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)", - memwrite_error_fatal) -) /* memwrite */ + .assert_reset = arm11_assert_reset, + .deassert_reset = arm11_deassert_reset, + .soft_reset_halt = arm11_soft_reset_halt, - RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)", - memrw_no_increment) + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)", - step_irq_enable) + .read_memory = arm11_read_memory, + .write_memory = arm11_write_memory, - RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register", - arm11_handle_vcr) + .bulk_write_memory = arm11_bulk_write_memory, - RC_FINAL("mrc", "Read Coprocessor register", - arm11_handle_mrc) + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, - RC_FINAL("mcr", "Write Coprocessor register", - arm11_handle_mcr) -) /* arm11 */ + .add_breakpoint = arm11_add_breakpoint, + .remove_breakpoint = arm11_remove_breakpoint, + .add_watchpoint = arm11_add_watchpoint, + .remove_watchpoint = arm11_remove_watchpoint, - return ERROR_OK; -} + .run_algorithm = armv4_5_run_algorithm, + + .commands = arm11_command_handlers, + .target_create = arm11_target_create, + .init_target = arm11_init_target, + .examine = arm11_examine, +};