X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=0f8faba33132b4f76a46d3411e767a6b06a0f57b;hp=4f7d37c667aaabdd9b744f7a46e4320c8be6dcef;hb=ed8fd94d7ca0fc0682de4020501afae89f31ccc3;hpb=88c91b4663ae5dca70ebbf52878904d23c98ead2

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 4f7d37c667..0f8faba331 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1,7 +1,8 @@
 /***************************************************************************
  *   Copyright (C) 2008 digenius technology GmbH.                          *
+ *   Michael Bruck                                                         *
  *                                                                         *
- *   Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com              *
+ *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
  *                                                                         *
  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
  *                                                                         *
@@ -26,11 +27,10 @@
 #endif
 
 #include "arm11.h"
-#include "jtag.h"
-#include "log.h"
+#include "armv4_5.h"
+#include "arm_simulator.h"
+#include "target_type.h"
 
-#include <stdlib.h>
-#include <string.h>
 
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
@@ -52,9 +52,10 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11);
 
 bool	arm11_config_memwrite_burst				= true;
 bool	arm11_config_memwrite_error_fatal		= true;
-u32		arm11_vcr								= 0;
+uint32_t		arm11_vcr								= 0;
 bool	arm11_config_memrw_no_increment			= false;
 bool	arm11_config_step_irq_enable			= false;
+bool	arm11_config_hardware_step				= false;
 
 #define ARM11_HANDLER(x)	\
 	.x				= arm11_##x
@@ -134,7 +135,7 @@ enum arm11_regtype
 typedef struct arm11_reg_defs_s
 {
 	char *					name;
-	u32						num;
+	uint32_t						num;
 	int						gdb_num;
 	enum arm11_regtype		type;
 } arm11_reg_defs_t;
@@ -290,14 +291,14 @@ enum arm11_regcache_ids
 
 #define ARM11_GDB_REGISTER_COUNT	26
 
-u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t arm11_gdb_dummy_fp_reg =
 {
 	"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
-u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
 reg_t arm11_gdb_dummy_fps_reg =
 {
@@ -313,18 +314,17 @@ reg_t arm11_gdb_dummy_fps_reg =
  *					available a pointer to a word holding the
  *					DSCR can be passed. Otherwise use NULL.
  */
-int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
 {
 	FNC_INFO;
-	int retval;
 
-	u32			dscr_local_tmp_copy;
+	uint32_t			dscr_local_tmp_copy;
 
 	if (!dscr)
 	{
 		dscr = &dscr_local_tmp_copy;
-		if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
-			return retval;
+
+		CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 	}
 
 	if (!(*dscr & ARM11_DSCR_MODE_SELECT))
@@ -341,7 +341,9 @@ int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
 		if (*dscr & ARM11_DSCR_CORE_HALTED)
 		{
 			/** \todo TODO: this needs further scrutiny because
-			  * arm11_on_enter_debug_state() never gets properly called
+			  * arm11_on_enter_debug_state() never gets properly called.
+			  * As a result we don't read the actual register states from
+			  * the target.
 			  */
 
 			arm11->target->state	= TARGET_HALTED;
@@ -372,19 +374,17 @@ int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
   */
 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 {
+	int retval;
 	FNC_INFO;
 
-	{size_t i;
-	for(i = 0; i < asizeof(arm11->reg_values); i++)
+	for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
 	{
 		arm11->reg_list[i].valid	= 1;
 		arm11->reg_list[i].dirty	= 0;
-	}}
+	}
 
 	/* Save DSCR */
-	int retval;
-	if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
-		return retval;
+	CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 
 	/* Save wDTR */
 
@@ -397,8 +397,8 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 		scan_field_t	chain5_fields[3];
 
 		arm11_setup_field(arm11, 32, NULL, &R(WDTR),	chain5_fields + 0);
-		arm11_setup_field(arm11,  1, NULL, NULL,	chain5_fields + 1);
-		arm11_setup_field(arm11,  1, NULL, NULL,	chain5_fields + 2);
+		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 1);
+		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 2);
 
 		arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 	}
@@ -412,7 +412,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 	/* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 	   ARM1136 seems to require this to issue ITR's as well */
 
-	u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
+	uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 
 	/* this executes JTAG queue: */
 
@@ -434,7 +434,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 		/* mcr	   15, 0, r0, cr7, cr10, {4} */
 		arm11_run_instr_no_data1(arm11, 0xee070f9a);
 
-		u32 dscr = arm11_read_DSCR(arm11);
+		uint32_t dscr = arm11_read_DSCR(arm11);
 
 		LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 
@@ -457,12 +457,13 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 
 	/** \todo TODO: handle other mode registers */
 
-	{size_t i;
-	for (i = 0; i < 15; i++)
+	for (size_t i = 0; i < 15; i++)
 	{
 		/* MCR p14,0,R?,c0,c5,0 */
-		arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
-	}}
+		retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
 	/* save rDTR */
 
@@ -486,7 +487,9 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 	/* save PC */
 
 	/* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
-	arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+	retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* adjust PC depending on ARM state */
 
@@ -531,27 +534,26 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
 		return;
 	}
 
-	{size_t i;
-	for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
+	for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 	{
 		if (!arm11->reg_list[i].valid)
 		{
 			if (arm11->reg_history[i].valid)
-				LOG_DEBUG("%8s INVALID	 (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+				LOG_DEBUG("%8s INVALID	 (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 		}
 		else
 		{
 			if (arm11->reg_history[i].valid)
 			{
 				if (arm11->reg_history[i].value != arm11->reg_values[i])
-					LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+					LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 			}
 			else
 			{
-				LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+				LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 			}
 		}
-	}}
+	}
 }
 
 /** Restore processor state
@@ -568,8 +570,8 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 	/** \todo TODO: handle other mode registers */
 
 	/* restore R1 - R14 */
-	{size_t i;
-	for (i = 1; i < 15; i++)
+
+	for (size_t i = 1; i < 15; i++)
 	{
 		if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 			continue;
@@ -578,23 +580,20 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 		arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 
 		//	LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
-	}}
+	}
 
 	arm11_run_instr_data_finish(arm11);
 
 	/* spec says clear wDTR and rDTR; we assume they are clear as
 	   otherwise our programming would be sloppy */
 	{
-		u32 DSCR;
-		int retval;
-		if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
-		{
-			return retval;
-		}
+		uint32_t DSCR;
+
+		CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 
 		if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 		{
-			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
+			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 		}
 	}
 
@@ -639,8 +638,8 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 
 		scan_field_t	chain5_fields[3];
 
-		u8			Ready		= 0;	/* ignored */
-		u8			Valid		= 0;	/* ignored */
+		uint8_t			Ready		= 0;	/* ignored */
+		uint8_t			Valid		= 0;	/* ignored */
 
 		arm11_setup_field(arm11, 32, &R(RDTR),	NULL, chain5_fields + 0);
 		arm11_setup_field(arm11,  1, &Ready,	NULL, chain5_fields + 1);
@@ -656,15 +655,14 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 
 void arm11_record_register_history(arm11_common_t * arm11)
 {
-	{size_t i;
-	for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
+	for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 	{
 		arm11->reg_history[i].value	= arm11->reg_values[i];
 		arm11->reg_history[i].valid	= arm11->reg_list[i].valid;
 
 		arm11->reg_list[i].valid	= 0;
 		arm11->reg_list[i].dirty	= 0;
-	}}
+	}
 }
 
 
@@ -672,21 +670,20 @@ void arm11_record_register_history(arm11_common_t * arm11)
 int arm11_poll(struct target_s *target)
 {
 	FNC_INFO;
+	int retval;
 
 	arm11_common_t * arm11 = target->arch_info;
 
 	if (arm11->trst_active)
 		return ERROR_OK;
 
-	u32	dscr;
-	int retval;
-	if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
-		return retval;
+	uint32_t	dscr;
 
-	LOG_DEBUG("DSCR %08x", dscr);
+	CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
-	if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
-		return retval;
+	LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
+
+	CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 
 	if (dscr & ARM11_DSCR_CORE_HALTED)
 	{
@@ -695,9 +692,11 @@ int arm11_poll(struct target_s *target)
 			enum target_state old_state = target->state;
 
 			LOG_DEBUG("enter TARGET_HALTED");
-			target->state		= TARGET_HALTED;
+			target->state			= TARGET_HALTED;
 			target->debug_reason	= arm11_get_DSCR_debug_reason(dscr);
-			arm11_on_enter_debug_state(arm11);
+			retval = arm11_on_enter_debug_state(arm11);
+			if (retval != ERROR_OK)
+				return retval;
 
 			target_call_event_callbacks(target,
 				old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
@@ -708,7 +707,7 @@ int arm11_poll(struct target_s *target)
 		if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 		{
 			LOG_DEBUG("enter TARGET_RUNNING");
-			target->state		= TARGET_RUNNING;
+			target->state			= TARGET_RUNNING;
 			target->debug_reason	= DBG_REASON_NOTHALTED;
 		}
 	}
@@ -720,8 +719,8 @@ int arm11_arch_state(struct target_s *target)
 {
 	arm11_common_t * arm11 = target->arch_info;
 
-	LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
-			 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
+	LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
+			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 			 R(CPSR),
 			 R(PC));
 
@@ -729,7 +728,7 @@ int arm11_arch_state(struct target_s *target)
 }
 
 /* target request support */
-int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
+int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
 {
 	FNC_INFO_NOTIMPLEMENTED;
 
@@ -739,14 +738,12 @@ int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
 /* target execution control */
 int arm11_halt(struct target_s *target)
 {
-	int retval = ERROR_OK;
-
 	FNC_INFO;
 
 	arm11_common_t * arm11 = target->arch_info;
 
 	LOG_DEBUG("target->state: %s",
-		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+		target_state_name(target));
 
 	if (target->state == TARGET_UNKNOWN)
 	{
@@ -767,19 +764,13 @@ int arm11_halt(struct target_s *target)
 
 	arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 
-	if((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(jtag_execute_queue());
 
-	u32 dscr;
+	uint32_t dscr;
 
 	while (1)
 	{
-		int retval;
-		retval = arm11_read_DSCR(arm11, &dscr);
-		if (retval!=ERROR_OK)
-			return retval;
+		CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
 		if (dscr & ARM11_DSCR_CORE_HALTED)
 			break;
@@ -792,19 +783,15 @@ int arm11_halt(struct target_s *target)
 	target->state		= TARGET_HALTED;
 	target->debug_reason	= arm11_get_DSCR_debug_reason(dscr);
 
-	if((retval = target_call_event_callbacks(target,
-		old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(
+		target_call_event_callbacks(target,
+			old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 
 	return ERROR_OK;
 }
 
-int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 {
-	int retval = ERROR_OK;
-
 	FNC_INFO;
 
 	//	  LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
@@ -813,7 +800,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 	arm11_common_t * arm11 = target->arch_info;
 
 	LOG_DEBUG("target->state: %s",
-		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+		target_state_name(target));
 
 
 	if (target->state != TARGET_HALTED)
@@ -825,7 +812,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 	if (!current)
 		R(PC) = address;
 
-	LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+	LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
 	/* clear breakpoints/watchpoints and VCR*/
 	arm11_sc7_clear_vbw(arm11);
@@ -841,7 +828,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 		{
 			if (bp->address == R(PC))
 			{
-				LOG_DEBUG("must step over %08x", bp->address);
+				LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 				arm11_step(target, 1, 0, 0);
 				break;
 			}
@@ -864,7 +851,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 			arm11_sc7_run(arm11, brp, asizeof(brp));
 
-			LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
+			LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 
 			brp_num++;
 		}
@@ -876,19 +863,15 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 
 	arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
-	if((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(jtag_execute_queue());
 
 	while (1)
 	{
-		u32 dscr;
-		retval = arm11_read_DSCR(arm11, &dscr);
-		if (retval!=ERROR_OK)
-			return retval;
+		uint32_t dscr;
 
-		LOG_DEBUG("DSCR %08x", dscr);
+		CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
+
+		LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 
 		if (dscr & ARM11_DSCR_CORE_RESTARTED)
 			break;
@@ -899,32 +882,112 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
 		target->state			= TARGET_RUNNING;
 		target->debug_reason	= DBG_REASON_NOTHALTED;
 
-		if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
-		{
-			return retval;
-		}
+		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 	}
 	else
 	{
 		target->state			= TARGET_DEBUG_RUNNING;
 		target->debug_reason	= DBG_REASON_NOTHALTED;
-		if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
-		{
-			return retval;
-		}
+
+		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 	}
 
 	return ERROR_OK;
 }
 
-int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+
+static int armv4_5_to_arm11(int reg)
 {
-	int retval = ERROR_OK;
+	if (reg < 16)
+		return reg;
+	switch (reg)
+	{
+	case ARMV4_5_CPSR:
+		return ARM11_RC_CPSR;
+	case 16:
+		/* FIX!!! handle thumb better! */
+		return ARM11_RC_CPSR;
+	default:
+		LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
+		exit(-1);
+	}
+}
+
+
+static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	reg=armv4_5_to_arm11(reg);
+
+	return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
+}
+
+static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	reg=armv4_5_to_arm11(reg);
+
+	buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
+}
+
+static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
+}
+
+static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
+{
+//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement thumb for arm11 */
+	return ARMV4_5_STATE_ARM;
+}
+
+static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+{
+//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement thumb for arm11 */
+	LOG_ERROR("Not implemetned!");
+}
+
+
+static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
+{
+	//arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement something that returns the current mode here!!! */
+	return ARMV4_5_MODE_USR;
+}
+
+static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
+{
+	struct arm_sim_interface sim;
 
+	sim.user_data=target->arch_info;
+	sim.get_reg=&arm11_sim_get_reg;
+	sim.set_reg=&arm11_sim_set_reg;
+	sim.get_reg_mode=&arm11_sim_get_reg;
+	sim.set_reg_mode=&arm11_sim_set_reg;
+	sim.get_cpsr=&arm11_sim_get_cpsr;
+	sim.get_mode=&arm11_sim_get_mode;
+	sim.get_state=&arm11_sim_get_state;
+	sim.set_state=&arm11_sim_set_state;
+
+	return arm_simulate_step_core(target, dry_run_pc, &sim);
+
+}
+
+int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+{
 	FNC_INFO;
 
 	LOG_DEBUG("target->state: %s",
-		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+		target_state_name(target));
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -937,14 +1000,14 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 	if (!current)
 		R(PC) = address;
 
-	LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
+	LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
+
 
 	/** \todo TODO: Thumb not supported here */
 
-	u32	next_instruction;
+	uint32_t	next_instruction;
 
-	if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
-		return retval;
+	CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
 
 	/* skip over BKPT */
 	if ((next_instruction & 0xFFF00070) == 0xe1200070)
@@ -952,7 +1015,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 		R(PC) += 4;
 		arm11->reg_list[ARM11_RC_PC].valid = 1;
 		arm11->reg_list[ARM11_RC_PC].dirty = 0;
-		LOG_INFO("Skipping BKPT");
+		LOG_DEBUG("Skipping BKPT");
 	}
 	/* skip over Wait for interrupt / Standby */
 	/* mcr	15, 0, r?, cr7, cr0, {4} */
@@ -961,12 +1024,12 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 		R(PC) += 4;
 		arm11->reg_list[ARM11_RC_PC].valid = 1;
 		arm11->reg_list[ARM11_RC_PC].dirty = 0;
-		LOG_INFO("Skipping WFI");
+		LOG_DEBUG("Skipping WFI");
 	}
 	/* ignore B to self */
 	else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 	{
-		LOG_INFO("Not stepping jump to self");
+		LOG_DEBUG("Not stepping jump to self");
 	}
 	else
 	{
@@ -983,13 +1046,32 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 
 		brp[0].write	= 1;
 		brp[0].address	= ARM11_SC7_BVR0;
-		brp[0].value	= R(PC);
 		brp[1].write	= 1;
 		brp[1].address	= ARM11_SC7_BCR0;
-		brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
 
-		if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
-			return retval;
+		if (arm11_config_hardware_step)
+		{
+			/* hardware single stepping be used if possible or is it better to
+			 * always use the same code path? Hardware single stepping is not supported
+			 * on all hardware
+			 */
+			 brp[0].value	= R(PC);
+			 brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+		} else
+		{
+			/* sets a breakpoint on the next PC(calculated by simulation),
+			 */
+			uint32_t next_pc;
+			int retval;
+			retval = arm11_simulate_step(target, &next_pc);
+			if (retval != ERROR_OK)
+				return retval;
+				
+			brp[0].value	= next_pc;
+			brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+		}
+
+		CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
 
 		/* resume */
 
@@ -1000,15 +1082,11 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 			R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 
 
-		if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
-			return retval;
+		CHECK_RETVAL(arm11_leave_debug_state(arm11));
 
 		arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 
-		if((retval = jtag_execute_queue()) != ERROR_OK)
-		{
-			return retval;
-		}
+		CHECK_RETVAL(jtag_execute_queue());
 
 		/** \todo TODO: add a timeout */
 
@@ -1016,12 +1094,11 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 
 		while (1)
 		{
-			u32 dscr;
-			retval = arm11_read_DSCR(arm11, &dscr);
-			if (retval!=ERROR_OK)
-				return retval;
+			uint32_t dscr;
+
+			CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
-			LOG_DEBUG("DSCR %08x", dscr);
+			LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
 
 			if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 				(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
@@ -1032,8 +1109,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 		arm11_sc7_clear_vbw(arm11);
 
 		/* save state */
-		if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
-			return retval;
+		CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
 
 	    /* restore default state */
 		R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
@@ -1043,10 +1119,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
 	//	  target->state		= TARGET_HALTED;
 	target->debug_reason	= DBG_REASON_SINGLESTEP;
 
-	if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
 	return ERROR_OK;
 }
@@ -1069,9 +1142,7 @@ int arm11_assert_reset(struct target_s *target)
 
 	if (target->reset_halt)
 	{
-		int retval;
-		if ((retval = target_halt(target))!=ERROR_OK)
-			return retval;
+		CHECK_RETVAL(target_halt(target));
 	}
 
 	return ERROR_OK;
@@ -1083,7 +1154,7 @@ int arm11_deassert_reset(struct target_s *target)
 
 #if 0
 	LOG_DEBUG("target->state: %s",
-		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
+		target_state_name(target));
 
 
 	/* deassert reset lines */
@@ -1116,22 +1187,20 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
 	*reg_list_size	= ARM11_GDB_REGISTER_COUNT;
 	*reg_list		= malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
 
-	{size_t i;
-	for (i = 16; i < 24; i++)
+	for (size_t i = 16; i < 24; i++)
 	{
 		(*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
-	}}
+	}
 
 	(*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
 
-	{size_t i;
-	for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
+	for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 	{
 		if (arm11_reg_defs[i].gdb_num == -1)
 			continue;
 
 		(*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
-	}}
+	}
 
 	return ERROR_OK;
 }
@@ -1140,9 +1209,9 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
  * count: number of items of <size>
  */
-int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	/** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
+	/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 
 	FNC_INFO;
 
@@ -1152,7 +1221,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -1167,20 +1236,19 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
 		/** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
 		arm11->reg_list[ARM11_RC_R1].dirty = 1;
 
-		{size_t i;
-		for (i = 0; i < count; i++)
+		for (size_t i = 0; i < count; i++)
 		{
 			/* ldrb    r1, [r0], #1 */
 			/* ldrb    r1, [r0] */
 			arm11_run_instr_no_data1(arm11,
 					!arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 
-			u32 res;
+			uint32_t res;
 			/* MCR p14,0,R1,c0,c5,0 */
 			arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 
 			*buffer++ = res;
-		}}
+		}
 
 		break;
 
@@ -1188,34 +1256,35 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
 		{
 			arm11->reg_list[ARM11_RC_R1].dirty = 1;
 
-			u16 * buf16 = (u16*)buffer;
-
-			{size_t i;
-			for (i = 0; i < count; i++)
+			for (size_t i = 0; i < count; i++)
 			{
 				/* ldrh    r1, [r0], #2 */
 				arm11_run_instr_no_data1(arm11,
 					!arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 
-				u32 res;
+				uint32_t res;
 
 				/* MCR p14,0,R1,c0,c5,0 */
 				arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 
-				*buf16++ = res;
-			}}
+				uint16_t svalue = res;
+				memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
+			}
 
 			break;
 		}
 
 	case 4:
+		{
+		uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+		/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+		uint32_t *words = (uint32_t *)buffer;
 
 		/* LDC p14,c5,[R0],#4 */
 		/* LDC p14,c5,[R0] */
-		arm11_run_instr_data_from_core(arm11,
-			(!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
-			(u32 *)buffer, count);
+		arm11_run_instr_data_from_core(arm11, instr, words, count);
 		break;
+		}
 	}
 
 	arm11_run_instr_data_finish(arm11);
@@ -1223,7 +1292,7 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
 	return ERROR_OK;
 }
 
-int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	FNC_INFO;
 
@@ -1233,7 +1302,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -1248,8 +1317,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 		{
 			arm11->reg_list[ARM11_RC_R1].dirty = 1;
 
-			{size_t i;
-			for (i = 0; i < count; i++)
+			for (size_t i = 0; i < count; i++)
 			{
 				/* MRC p14,0,r1,c0,c5,0 */
 				arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
@@ -1258,7 +1326,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 				/* strb    r1, [r0] */
 				arm11_run_instr_no_data1(arm11,
 					!arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
-			}}
+			}
 
 			break;
 		}
@@ -1267,58 +1335,58 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 		{
 			arm11->reg_list[ARM11_RC_R1].dirty = 1;
 
-			u16 * buf16 = (u16*)buffer;
-
-			{size_t i;
-			for (i = 0; i < count; i++)
+			for (size_t i = 0; i < count; i++)
 			{
+				uint16_t value;
+				memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
+
 				/* MRC p14,0,r1,c0,c5,0 */
-				arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
+				arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
 
 				/* strh    r1, [r0], #2 */
 				/* strh    r1, [r0] */
 				arm11_run_instr_no_data1(arm11,
 					!arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
-			}}
+			}
 
 			break;
 		}
 
-	case 4:
-		/** \todo TODO: check if buffer cast to u32* might cause alignment problems */
+	case 4: {
+		uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+
+		/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+		uint32_t *words = (uint32_t*)buffer;
 
 		if (!arm11_config_memwrite_burst)
 		{
 			/* STC p14,c5,[R0],#4 */
 			/* STC p14,c5,[R0]*/
-			arm11_run_instr_data_to_core(arm11,
-				(!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
-				(u32 *)buffer, count);
+			arm11_run_instr_data_to_core(arm11, instr, words, count);
 		}
 		else
 		{
 			/* STC p14,c5,[R0],#4 */
 			/* STC p14,c5,[R0]*/
-			arm11_run_instr_data_to_core_noack(arm11,
-				(!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
-				(u32 *)buffer, count);
+			arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
 		}
 
 		break;
 	}
+	}
 
 #if 1
 	/* r0 verification */
 	if (!arm11_config_memrw_no_increment)
 	{
-		u32 r0;
+		uint32_t r0;
 
 		/* MCR p14,0,R0,c0,c5,0 */
 		arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
 
 		if (address + size * count != r0)
 		{
-			LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
+			LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
 
 			if (arm11_config_memwrite_burst)
 				LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
@@ -1336,7 +1404,7 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
 
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
+int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	FNC_INFO;
 
@@ -1349,11 +1417,13 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8
 	return arm11_write_memory(target, address, 4, count, buffer);
 }
 
-int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+/* here we have nothing target specific to contribute, so we fail and then the
+ * fallback code will read data from the target and calculate the CRC on the
+ * host.
+ */
+int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
 {
-	FNC_INFO_NOTIMPLEMENTED;
-
-	return ERROR_OK;
+	return ERROR_FAIL;
 }
 
 /* target break-/watchpoint control
@@ -1375,13 +1445,13 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
 	if (!arm11->free_brps)
 	{
-		LOG_INFO("no breakpoint unit available for hardware breakpoint");
+		LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	if (breakpoint->length != 4)
 	{
-		LOG_INFO("only breakpoints of four bytes length supported");
+		LOG_DEBUG("only breakpoints of four bytes length supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -1418,25 +1488,18 @@ int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 // HACKHACKHACK - FIXME mode/state
 /* target algorithm support */
 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
-			int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
+			int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
 			int timeout_ms, void *arch_info)
 {
 		arm11_common_t *arm11 = target->arch_info;
-	armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
 //	enum armv4_5_state core_state = arm11->core_state;
 //	enum armv4_5_mode core_mode = arm11->core_mode;
-	u32 context[16];
-	u32 cpsr;
+	uint32_t context[16];
+	uint32_t cpsr;
 	int exit_breakpoint_size = 0;
-	int i;
 	int retval = ERROR_OK;
 		LOG_DEBUG("Running algorithm");
 
-	if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
-	{
-		LOG_ERROR("current target isn't an ARMV4/5 target");
-		return ERROR_TARGET_INVALID;
-	}
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -1449,22 +1512,22 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 //		return ERROR_FAIL;
 
 	// Save regs
-	for (i = 0; i < 16; i++)
+	for (size_t i = 0; i < 16; i++)
 	{
-		context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
-		LOG_DEBUG("Save %i: 0x%x",i,context[i]);
+		context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
+		LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
 	}
 
-	cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
-	LOG_DEBUG("Save CPSR: 0x%x", cpsr);
+	cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
+	LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
 
-	for (i = 0; i < num_mem_params; i++)
+	for (int i = 0; i < num_mem_params; i++)
 	{
 		target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 	}
 
 	// Set register parameters
-	for (i = 0; i < num_reg_params; i++)
+	for (int i = 0; i < num_reg_params; i++)
 	{
 		reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
 		if (!reg)
@@ -1495,6 +1558,12 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 		exit(-1);
 	}
 */
+
+
+/* arm11 at this point only supports ARM not THUMB mode
+   however if this test needs to be reactivated the current state can be read back
+   from CPSR */
+#if 0
 	if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
 	{
 		LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
@@ -1502,6 +1571,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 		arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
 		arm11->reg_list[ARM11_RC_CPSR].valid = 1;
 	}
+#endif
 
 	if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
 	{
@@ -1511,43 +1581,36 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t
 	}
 
 	// no debug, otherwise breakpoint is not set
-	if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
 
-	if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
-	{
-		return retval;
-	}
+	CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
 
 	if (target->state != TARGET_HALTED)
 	{
-		if ((retval=target_halt(target))!=ERROR_OK)
-			return retval;
-		if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
-		{
-			return retval;
-		}
+		CHECK_RETVAL(target_halt(target));
+
+		CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
+
 		retval = ERROR_TARGET_TIMEOUT;
+
 		goto del_breakpoint;
 	}
 
 	if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
 	{
-		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
 			buf_get_u32(arm11->reg_list[15].value, 0, 32));
 		retval = ERROR_TARGET_TIMEOUT;
 		goto del_breakpoint;
 	}
 
-	for (i = 0; i < num_mem_params; i++)
+	for (int i = 0; i < num_mem_params; i++)
 	{
 		if (mem_params[i].direction != PARAM_OUT)
 			target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 	}
 
-	for (i = 0; i < num_reg_params; i++)
+	for (int i = 0; i < num_reg_params; i++)
 	{
 		if (reg_params[i].direction != PARAM_OUT)
 		{
@@ -1573,14 +1636,14 @@ del_breakpoint:
 
 restore:
 	// Restore context
-	for (i = 0; i < 16; i++)
+	for (size_t i = 0; i < 16; i++)
 	{
-		LOG_DEBUG("restoring register %s with value 0x%8.8x",
+		LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
 			 arm11->reg_list[i].name, context[i]);
-		arm11_set_reg(&arm11->reg_list[i], (u8*)&context[i]);
+		arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
 	}
-	LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
-	arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (u8*)&cpsr);
+	LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
+	arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
 
 //	arm11->core_state = core_state;
 //	arm11->core_mode = core_mode;
@@ -1590,23 +1653,13 @@ restore:
 
 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
 {
-	int retval = ERROR_OK;
 	FNC_INFO;
 
 	NEW(arm11_common_t, arm11, 1);
 
 	arm11->target = target;
 
-	/* prepare JTAG information for the new target */
-	arm11->jtag_info.tap	= target->tap;
-	arm11->jtag_info.scann_size	= 5;
-
-	if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
-	{
-		return retval;
-	}
-
-	if (target->tap==NULL)
+	if (target->tap == NULL)
 		return ERROR_FAIL;
 
 	if (target->tap->ir_length != 5)
@@ -1630,7 +1683,6 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
 int arm11_examine(struct target_s *target)
 {
 	FNC_INFO;
-	int retval;
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -1657,9 +1709,7 @@ int arm11_examine(struct target_s *target)
 
 	arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
 
-	if ((retval=jtag_execute_queue())!=ERROR_OK)
-		return retval;
-
+	CHECK_RETVAL(jtag_execute_queue());
 
 	switch (arm11->device_id & 0x0FFFF000)
 	{
@@ -1689,9 +1739,9 @@ int arm11_examine(struct target_s *target)
 	arm11->free_brps = arm11->brp;
 	arm11->free_wrps = arm11->wrp;
 
-	LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
+	LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
 		arm11->device_id,
-		arm11->implementor,
+		(int)(arm11->implementor),
 		arm11->didr);
 
 	/* as a side-effect this reads DSCR and thus
@@ -1701,7 +1751,7 @@ int arm11_examine(struct target_s *target)
 
 	arm11_check_init(arm11, NULL);
 
-	target->type->examined = 1;
+	target_set_examined(target);
 
 	return ERROR_OK;
 }
@@ -1737,7 +1787,7 @@ int arm11_get_reg(reg_t *reg)
 }
 
 /** Change a value in the register cache */
-int arm11_set_reg(reg_t *reg, u8 *buf)
+int arm11_set_reg(reg_t *reg, uint8_t *buf)
 {
 	FNC_INFO;
 
@@ -1799,7 +1849,7 @@ int arm11_build_reg_cache(target_t *target)
 
 		r->name				= rd->name;
 		r->size				= 32;
-		r->value			= (u8 *)(arm11->reg_values + i);
+		r->value			= (uint8_t *)(arm11->reg_values + i);
 		r->dirty			= 0;
 		r->valid			= 0;
 		r->bitfield_desc	= NULL;
@@ -1872,6 +1922,7 @@ BOOL_WRAPPER(memwrite_burst,			"memory write burst mode")
 BOOL_WRAPPER(memwrite_error_fatal,		"fatal error mode for memory writes")
 BOOL_WRAPPER(memrw_no_increment,		"\"no increment\" mode for memory transfers")
 BOOL_WRAPPER(step_irq_enable,			"IRQs while stepping")
+BOOL_WRAPPER(hardware_step,			"hardware single step")
 
 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
@@ -1884,11 +1935,11 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args,
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	LOG_INFO("VCR 0x%08X", arm11_vcr);
+	LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
 	return ERROR_OK;
 }
 
-const u32 arm11_coproc_instruction_limits[] =
+const uint32_t arm11_coproc_instruction_limits[] =
 {
 	15,				/* coprocessor */
 	7,				/* opcode 1 */
@@ -1906,7 +1957,7 @@ arm11_common_t * arm11_find_target(const char * arg)
 	jtag_tap_t *	tap;
 	target_t *		t;
 
-	tap = jtag_TapByString(arg);
+	tap = jtag_tap_by_string(arg);
 
 	if (!tap)
 		return 0;
@@ -1917,7 +1968,7 @@ arm11_common_t * arm11_find_target(const char * arg)
 			continue;
 
 		/* if (t->type == arm11_target) */
-		if (0 == strcmp(t->type->name, "arm11"))
+		if (0 == strcmp(target_get_name(t), "arm11"))
 			return t->arch_info;
 	}
 
@@ -1948,23 +1999,23 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	u32	values[6];
+	uint32_t	values[6];
 
-	{size_t i;
-	for (i = 0; i < (read ? 5 : 6); i++)
+	for (size_t i = 0; i < (read ? 5 : 6); i++)
 	{
 		values[i] = strtoul(args[i + 1], NULL, 0);
 
 		if (values[i] > arm11_coproc_instruction_limits[i])
 		{
-			LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
-				(long)(i + 2), arm11_coproc_instruction_limits[i],
+			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+				  (long)(i + 2),
+				  arm11_coproc_instruction_limits[i],
 				read ? arm11_mrc_syntax : arm11_mcr_syntax);
 			return -1;
 		}
-	}}
+	}
 
-	u32 instr = 0xEE000010	|
+	uint32_t instr = 0xEE000010	|
 		(values[0] <<  8) |
 		(values[1] << 21) |
 		(values[2] << 16) |
@@ -1978,20 +2029,24 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
 
 	if (read)
 	{
-		u32 result;
+		uint32_t result;
 		arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
 
-		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
-			values[0], values[1], values[2], values[3], values[4], result, result);
+		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
+			 (int)(values[0]),
+			 (int)(values[1]),
+			 (int)(values[2]),
+			 (int)(values[3]),
+			 (int)(values[4]), result, result);
 	}
 	else
 	{
 		arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
 
-		LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
-			values[0], values[1],
-			values[5],
-			values[2], values[3], values[4]);
+		LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
+			 (int)(values[0]), (int)(values[1]),
+			 values[5],
+			 (int)(values[2]), (int)(values[3]), (int)(values[4]));
 	}
 
 	arm11_run_instr_data_finish(arm11);
@@ -2016,32 +2071,34 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 
 	command_t * top_cmd = NULL;
 
-	RC_TOP(				"arm11",				"arm11 specific commands",
+	RC_TOP("arm11",				"arm11 specific commands",
 
-	RC_TOP(				"memwrite",				"Control memory write transfer mode",
+	RC_TOP("memwrite",				"Control memory write transfer mode",
 
-		RC_FINAL_BOOL(	"burst",				"Enable/Disable non-standard but fast burst mode (default: enabled)",
+		RC_FINAL_BOOL("burst",				"Enable/Disable non-standard but fast burst mode (default: enabled)",
 						memwrite_burst)
 
-		RC_FINAL_BOOL(	"error_fatal",			"Terminate program if transfer error was found (default: enabled)",
+		RC_FINAL_BOOL("error_fatal",			"Terminate program if transfer error was found (default: enabled)",
 						memwrite_error_fatal)
-	)
+) /* memwrite */
 
-	RC_FINAL_BOOL(		"no_increment",			"Don't increment address on multi-read/-write (default: disabled)",
+	RC_FINAL_BOOL("no_increment",			"Don't increment address on multi-read/-write (default: disabled)",
 						memrw_no_increment)
 
-	RC_FINAL_BOOL(		"step_irq_enable",		"Enable interrupts while stepping (default: disabled)",
-						step_irq_enable)
+RC_FINAL_BOOL("step_irq_enable",		"Enable interrupts while stepping (default: disabled)",
+					step_irq_enable)
+RC_FINAL_BOOL("hardware_step",		"hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
+					hardware_step)
 
-	RC_FINAL(			"vcr",					"Control (Interrupt) Vector Catch Register",
+	RC_FINAL("vcr",					"Control (Interrupt) Vector Catch Register",
 						arm11_handle_vcr)
 
-	RC_FINAL(			"mrc",					"Read Coprocessor register",
+	RC_FINAL("mrc",					"Read Coprocessor register",
 						arm11_handle_mrc)
 
-	RC_FINAL(			"mcr",					"Write Coprocessor register",
+	RC_FINAL("mcr",					"Write Coprocessor register",
 						arm11_handle_mcr)
-	)
+) /* arm11 */
 
 	return ERROR_OK;
 }