X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm.h;h=ea83d386736569a2b6bc918e02047a4f0305ab96;hp=d97a95edf934a0e6fbeeb102e32b62cec7bfb658;hb=HEAD;hpb=f2c83fade3ea7e51e5c9283aa3ff94632a41cc55 diff --git a/src/target/arm.h b/src/target/arm.h index d97a95edf9..486666b5c6 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + /* * Copyright (C) 2005 by Dominic Rath * Dominic.Rath@gmx.de @@ -10,19 +12,6 @@ * * Copyright (C) 2018 by Liviu Ionescu * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . */ #ifndef OPENOCD_TARGET_ARM_H @@ -60,6 +49,22 @@ enum arm_core_type { ARM_CORE_TYPE_M_PROFILE, }; +/** ARM Architecture specifying the version and the profile */ +enum arm_arch { + ARM_ARCH_UNKNOWN, + ARM_ARCH_V4, + ARM_ARCH_V6M, + ARM_ARCH_V7M, + ARM_ARCH_V8M, +}; + +/** Known ARM implementor IDs */ +enum arm_implementor { + ARM_IMPLEMENTOR_ARM = 0x41, + ARM_IMPLEMENTOR_INFINEON = 0x49, + ARM_IMPLEMENTOR_REALTEK = 0x72, +}; + /** * Represent state of an ARM core. * @@ -157,7 +162,7 @@ enum arm_vfp_version { ARM_VFP_V3, }; -#define ARM_COMMON_MAGIC 0x0A450A45 +#define ARM_COMMON_MAGIC 0x0A450A45U /** * Represents a generic ARM core, with standard application registers. @@ -167,7 +172,8 @@ enum arm_vfp_version { * registers as traditional ARM cores, and only support Thumb2 instructions. */ struct arm { - int common_magic; + unsigned int common_magic; + struct reg_cache *core_cache; /** Handle to the PC; valid in all core modes. */ @@ -191,14 +197,8 @@ struct arm { /** Record the current core state: ARM, Thumb, or otherwise. */ enum arm_state core_state; - /** Flag reporting unavailability of the BKPT instruction. */ - bool is_armv4; - - /** Flag reporting armv6m based core. */ - bool is_armv6m; - - /** Flag reporting armv8m based core. */ - bool is_armv8m; + /** ARM architecture version */ + enum arm_arch arch; /** Floating point or VFP version, 0 if disabled. */ int arm_vfp_version; @@ -228,15 +228,25 @@ struct arm { /** Read coprocessor register. */ int (*mrc)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t *value); + /** Read coprocessor to two registers. */ + int (*mrrc)(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t *value); + /** Write coprocessor register. */ int (*mcr)(struct target *target, int cpnum, uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, + uint32_t crn, uint32_t crm, uint32_t value); + /** Write coprocessor from two registers. */ + int (*mcrr)(struct target *target, int cpnum, + uint32_t op, uint32_t crm, + uint64_t value); + void *arch_info; /** For targets conforming to ARM Debug Interface v5, @@ -247,20 +257,20 @@ struct arm { }; /** Convert target handle to generic ARM target state handle. */ -static inline struct arm *target_to_arm(struct target *target) +static inline struct arm *target_to_arm(const struct target *target) { - assert(target != NULL); + assert(target); return target->arch_info; } static inline bool is_arm(struct arm *arm) { - assert(arm != NULL); + assert(arm); return arm->common_magic == ARM_COMMON_MAGIC; } struct arm_algorithm { - int common_magic; + unsigned int common_magic; enum arm_mode core_mode; enum arm_state core_state; @@ -280,13 +290,14 @@ void arm_free_reg_cache(struct arm *arm); struct reg_cache *armv8_build_reg_cache(struct target *target); extern const struct command_registration arm_command_handlers[]; +extern const struct command_registration arm_all_profiles_command_handlers[]; int arm_arch_state(struct target *target); -const char *arm_get_gdb_arch(struct target *target); +const char *arm_get_gdb_arch(const struct target *target); int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); -const char *armv8_get_gdb_arch(struct target *target); +const char *armv8_get_gdb_arch(const struct target *target); int armv8_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size, enum target_register_class reg_class); @@ -298,14 +309,14 @@ int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, target_addr_t entry_point, target_addr_t exit_point, - int timeout_ms, void *arch_info); + unsigned int timeout_ms, void *arch_info); int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info, + unsigned int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, - int timeout_ms, void *arch_info)); + unsigned int timeout_ms, void *arch_info)); int arm_checksum_memory(struct target *target, target_addr_t address, uint32_t count, uint32_t *checksum); @@ -316,7 +327,4 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr); struct reg *arm_reg_current(struct arm *arm, unsigned regnum); struct reg *armv8_reg_current(struct arm *arm, unsigned regnum); -extern struct reg arm_gdb_dummy_fp_reg; -extern struct reg arm_gdb_dummy_fps_reg; - #endif /* OPENOCD_TARGET_ARM_H */