X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm.h;h=226dd65689a15add147d39c3ac652b885e6edd09;hp=00dbe2d6f4cd9abb305c8e764074cf402bd08041;hb=c0e7ccbd87cf491b065bf18bbdb6a73b741c2698;hpb=0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d;ds=sidebyside
diff --git a/src/target/arm.h b/src/target/arm.h
index 00dbe2d6f4..226dd65689 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -19,15 +19,14 @@
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the
- * Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * along with this program. If not, see .
*/
-#ifndef ARM_H
-#define ARM_H
-#include
+#ifndef OPENOCD_TARGET_ARM_H
+#define OPENOCD_TARGET_ARM_H
+
#include
+#include "target.h"
/**
@@ -40,19 +39,33 @@
*/
/**
- * These numbers match the five low bits of the *PSR registers on
+ * Represent state of an ARM core.
+ *
+ * Most numbers match the five low bits of the *PSR registers on
* "classic ARM" processors, which build on the ARMv4 processor
* modes and register set.
+ *
+ * ARM_MODE_ANY is a magic value, often used as a wildcard.
+ *
+ * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
+ * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
+ * they support.
*/
enum arm_mode {
ARM_MODE_USR = 16,
ARM_MODE_FIQ = 17,
ARM_MODE_IRQ = 18,
ARM_MODE_SVC = 19,
+ ARM_MODE_MON = 22,
ARM_MODE_ABT = 23,
- ARM_MODE_MON = 26,
ARM_MODE_UND = 27,
+ ARM_MODE_1176_MON = 28,
ARM_MODE_SYS = 31,
+
+ ARM_MODE_THREAD = 0,
+ ARM_MODE_USER_THREAD = 1,
+ ARM_MODE_HANDLER = 2,
+
ARM_MODE_ANY = -1
};
@@ -67,8 +80,6 @@ enum arm_state {
ARM_STATE_THUMB_EE,
};
-extern const char *arm_state_strings[];
-
#define ARM_COMMON_MAGIC 0x0A450A45
/**
@@ -82,7 +93,10 @@ struct arm {
int common_magic;
struct reg_cache *core_cache;
- /** Handle to the CPSR; valid in all core modes. */
+ /** Handle to the PC; valid in all core modes. */
+ struct reg *pc;
+
+ /** Handle to the CPSR/xPSR; valid in all core modes. */
struct reg *cpsr;
/** Handle to the SPSR; valid only in core modes with an SPSR. */
@@ -96,6 +110,8 @@ struct arm {
* ARM_MODE_ANY indicates the standard set of 37 registers,
* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
* more registers are shadowed, for "Secure Monitor" mode.
+ * ARM_MODE_THREAD indicates a microcontroller profile core,
+ * which only shadows SP.
*/
enum arm_mode core_type;
@@ -108,12 +124,29 @@ struct arm {
/** Flag reporting unavailability of the BKPT instruction. */
bool is_armv4;
+ /** Flag reporting armv6m based core. */
+ bool is_armv6m;
+
/** Flag reporting whether semihosting is active. */
bool is_semihosting;
+ /** Flag reporting whether semihosting fileio is active. */
+ bool is_semihosting_fileio;
+
+ /** Flag reporting whether semihosting fileio operation is active. */
+ bool semihosting_hit_fileio;
+
+ /** Current semihosting operation. */
+ int semihosting_op;
+
+ /** Current semihosting result. */
+ int semihosting_result;
+
/** Value to be returned by semihosting SYS_ERRNO request. */
int semihosting_errno;
+ int (*setup_semihosting)(struct target *target, int enable);
+
/** Backpointer to the target. */
struct target *target;
@@ -132,7 +165,7 @@ struct arm {
int (*read_core_reg)(struct target *target, struct reg *reg,
int num, enum arm_mode mode);
int (*write_core_reg)(struct target *target, struct reg *reg,
- int num, enum arm_mode mode, uint32_t value);
+ int num, enum arm_mode mode, uint8_t *value);
/** Read coprocessor register. */
int (*mrc)(struct target *target, int cpnum,
@@ -147,17 +180,25 @@ struct arm {
uint32_t value);
void *arch_info;
+
+ /** For targets conforming to ARM Debug Interface v5,
+ * this handle references the Debug Access Port (DAP)
+ * used to make requests to the target.
+ */
+ struct adiv5_dap *dap;
};
/** Convert target handle to generic ARM target state handle. */
static inline struct arm *target_to_arm(struct target *target)
{
+ assert(target != NULL);
return target->arch_info;
}
static inline bool is_arm(struct arm *arm)
{
- return arm && arm->common_magic == ARM_COMMON_MAGIC;
+ assert(arm != NULL);
+ return arm->common_magic == ARM_COMMON_MAGIC;
}
struct arm_algorithm {
@@ -171,8 +212,8 @@ struct arm_reg {
int num;
enum arm_mode mode;
struct target *target;
- struct arm *armv4_5_common;
- uint32_t value;
+ struct arm *arm;
+ uint8_t value[4];
};
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
@@ -181,7 +222,8 @@ extern const struct command_registration arm_command_handlers[];
int arm_arch_state(struct target *target);
int arm_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int arm_init_arch_info(struct target *target, struct arm *arm);
@@ -191,11 +233,18 @@ int armv4_5_run_algorithm(struct target *target,
int num_reg_params, struct reg_param *reg_params,
uint32_t entry_point, uint32_t exit_point,
int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm_inner(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info,
+ int (*run_it)(struct target *target, uint32_t exit_point,
+ int timeout_ms, void *arch_info));
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum);
int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
+ uint32_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
@@ -203,4 +252,4 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
extern struct reg arm_gdb_dummy_fp_reg;
extern struct reg arm_gdb_dummy_fps_reg;
-#endif /* ARM_H */
+#endif /* OPENOCD_TARGET_ARM_H */