X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fadi_v5_jtag.c;h=b71fe3820ea53e20d02041a98164b61b1c448612;hp=41443ff2fe5b4d898a6309f95369bc7e24d909bc;hb=830d0c55c0920606366a15560d1945f1e1942744;hpb=c09035ea2cb24dee300476a3502919d23d90d1f5

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 41443ff2fe..b71fe3820e 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -23,7 +23,7 @@
  *   You should have received a copy of the GNU General Public License
  *   along with this program; if not, write to the
  *   Free Software Foundation, Inc.,
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  ***************************************************************************/
 
 /**
@@ -40,7 +40,6 @@
 #include "arm_adi_v5.h"
 #include <helper/time_support.h>
 
-
 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
 #define JTAG_DP_ABORT		0x8
 #define JTAG_DP_DPACC		0xA
@@ -51,6 +50,8 @@
 #define JTAG_ACK_OK_FAULT	0x2
 #define JTAG_ACK_WAIT		0x1
 
+static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
+
 /***************************************************************************
  *
  * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
@@ -66,7 +67,7 @@
  * will be needed to collect the data which was read; the "invalue" collects
  * the posted result of a preceding operation, not the current one.
  *
- * @param swjdp the DAP
+ * @param dap the DAP
  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
  *	SELECT register has more addressing bits.
@@ -74,21 +75,22 @@
  * @param outvalue points to a 32-bit (little-endian) integer
  * @param invalue NULL, or points to a 32-bit (little-endian) integer
  * @param ack points to where the three bit JTAG_ACK_* code will be stored
+ * @param memaccess_tck number of idle cycles to add after AP access
  */
 
-/* FIXME don't export ... this is a temporary workaround for the
- * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
- */
-int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+static int adi_jtag_dp_scan(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
+		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack,
+		uint32_t memaccess_tck)
 {
-	struct arm_jtag *jtag_info = swjdp->jtag_info;
+	struct jtag_tap *tap = dap->tap;
 	struct scan_field fields[2];
 	uint8_t out_addr_buf;
+	int retval;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(tap, instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Scan out a read or write operation using some DP or AP register.
 	 * For APACC access with any sticky error flag set, this is discarded.
@@ -107,7 +109,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 	fields[1].out_value = outvalue;
 	fields[1].in_value = invalue;
 
-	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
+	jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 
 	/* Add specified number of tck clocks after starting memory bus
 	 * access, giving the hardware time to complete the access.
@@ -115,13 +117,12 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 	 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 	 */
 	if ((instr == JTAG_DP_APACC)
-			&& ((reg_addr == AP_REG_DRW)
-				|| ((reg_addr & 0xF0) == AP_REG_BD0))
-			&& (swjdp->memaccess_tck != 0))
-		jtag_add_runtest(swjdp->memaccess_tck,
-				TAP_IDLE);
+			&& ((reg_addr == MEM_AP_REG_DRW)
+				|| ((reg_addr & 0xF0) == MEM_AP_REG_BD0))
+			&& memaccess_tck != 0)
+		jtag_add_runtest(memaccess_tck, TAP_IDLE);
 
-	return jtag_get_error();
+	return ERROR_OK;
 }
 
 /**
@@ -130,17 +131,18 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
  * conversions are performed (so the types of invalue and outvalue
  * must be different).
  */
-static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
+		uint32_t outvalue, uint32_t *invalue, uint8_t *ack,
+		uint32_t memaccess_tck)
 {
 	uint8_t out_value_buf[4];
 	int retval;
 
 	buf_set_u32(out_value_buf, 0, 32, outvalue);
 
-	retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
-			out_value_buf, (uint8_t *)invalue, ack);
+	retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
+			out_value_buf, (uint8_t *)invalue, ack, memaccess_tck);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -154,22 +156,22 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
 /**
  * Utility to write AP registers.
  */
-static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
+static inline int adi_jtag_ap_write_check(struct adiv5_ap *ap,
 		uint8_t reg_addr, uint8_t *outvalue)
 {
-	return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
-			outvalue, NULL, NULL);
+	return adi_jtag_dp_scan(ap->dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
+			outvalue, NULL, NULL, ap->memaccess_tck);
 }
 
-static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint32_t outvalue, uint32_t *invalue)
+		uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
 {
 	int retval;
 
 	/* Issue the read or write */
-	retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
-			RnW, outvalue, NULL, NULL);
+	retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
+			RnW, outvalue, NULL, NULL, memaccess_tck);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -177,107 +179,103 @@ static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
 	 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 	 */
 	if ((RnW == DPAP_READ) && (invalue != NULL))
-		retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
-				DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+		retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
+				DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack, 0);
 	return retval;
 }
 
-static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
+static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 {
 	int retval;
 	uint32_t ctrlstat;
 
 	/* too expensive to call keep_alive() here */
 
-#if 0
-	/* Danger!!!! BROKEN!!!! */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-	/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
-	R956 introduced the check on return value here and now Michael Schwingen reports
-	that this code no longer works....
-
-	https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
-	*/
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("BUG: Why does this fail the first time????");
-	}
-	/* Why??? second time it works??? */
-#endif
+	/* Here be dragons!
+	 *
+	 * It is easy to be in a JTAG clock range where the target
+	 * is not operating in a stable fashion. This happens
+	 * for a few reasons:
+	 *
+	 * - the user may construct a simple test case to try to see
+	 * if a higher JTAG clock works to eke out more performance.
+	 * This simple case may pass, but more complex situations can
+	 * fail.
+	 *
+	 * - The mostly works JTAG clock rate and the complete failure
+	 * JTAG clock rate may be as much as 2-4x apart. This seems
+	 * to be especially true on RC oscillator driven parts.
+	 *
+	 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
+	 * times here seems to "make things better here", it is just
+	 * hiding problems with too high a JTAG clock.
+	 *
+	 * Note that even if some parts have RCLK/RTCK, that doesn't
+	 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
+	 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
+	 * before the RC oscillator phase is not yet complete.
+	 */
 
 	/* Post CTRL/STAT read; discard any previous posted read value
 	 * but collect its ACK status.
 	 */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
 		return retval;
 
-	swjdp->ack = swjdp->ack & 0x7;
+	dap->ack = dap->ack & 0x7;
 
 	/* common code path avoids calling timeval_ms() */
-	if (swjdp->ack != JTAG_ACK_OK_FAULT)
-	{
+	if (dap->ack != JTAG_ACK_OK_FAULT) {
 		long long then = timeval_ms();
 
-		while (swjdp->ack != JTAG_ACK_OK_FAULT)
-		{
-			if (swjdp->ack == JTAG_ACK_WAIT)
-			{
-				if ((timeval_ms()-then) > 1000)
-				{
-					/* NOTE:  this would be a good spot
-					 * to use JTAG_DP_ABORT.
-					 */
+		while (dap->ack != JTAG_ACK_OK_FAULT) {
+			if (dap->ack == JTAG_ACK_WAIT) {
+				if ((timeval_ms()-then) > 1000) {
 					LOG_WARNING("Timeout (1000ms) waiting "
 						"for ACK=OK/FAULT "
-						"in JTAG-DP transaction");
+						"in JTAG-DP transaction - aborting");
+
+					uint8_t ack;
+					int abort_ret = jtag_ap_q_abort(dap, &ack);
+
+					if (abort_ret != 0)
+						LOG_WARNING("Abort failed : return=%d ack=%d", abort_ret, ack);
+
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
-			}
-			else
-			{
+			} else {
 				LOG_WARNING("Invalid ACK %#x "
 						"in JTAG-DP transaction",
-						swjdp->ack);
+						dap->ack);
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = jtag_execute_queue();
+			if (retval != ERROR_OK)
 				return retval;
-			swjdp->ack = swjdp->ack & 0x7;
+			dap->ack = dap->ack & 0x7;
 		}
 	}
 
 	/* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 
 	/* Check for STICKYERR and STICKYORUN */
-	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
-	{
+	if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
 		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 		/* Check power to debug regions */
-		if ((ctrlstat & 0xf0000000) != 0xf0000000)
-			 ahbap_debugport_init(swjdp);
-		else
-		{
-			uint32_t mem_ap_csw, mem_ap_tar;
-
-			/* Maybe print information about last intended
-			 * MEM-AP access; but not if autoincrementing.
-			 * *Real* CSW and TAR values are always shown.
-			 */
-			if (swjdp->ap_tar_value != (uint32_t) -1)
-				LOG_DEBUG("MEM-AP Cached values: "
-					"ap_bank 0x%" PRIx32
-					", ap_csw 0x%" PRIx32
-					", ap_tar 0x%" PRIx32,
-					swjdp->ap_bank_value,
-					swjdp->ap_csw_value,
-					swjdp->ap_tar_value);
-
+		if ((ctrlstat & 0xf0000000) != 0xf0000000) {
+			LOG_ERROR("Debug regions are unpowered, an unexpected reset might have happened");
+			return ERROR_JTAG_DEVICE_ERROR;
+		} else {
 			if (ctrlstat & SSTICKYORUN)
 				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 					"memaccess, or reduce jtag speed");
@@ -286,34 +284,24 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 				LOG_ERROR("JTAG-DP STICKY ERROR");
 
 			/* Clear Sticky Error Bits */
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_WRITE,
-					swjdp->dp_ctrl_stat | SSTICKYORUN
-						| SSTICKYERR, NULL);
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
-				return retval;
-
-			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
-
-			retval = dap_queue_ap_read(swjdp,
-					AP_REG_CSW, &mem_ap_csw);
+					dap->dp_ctrl_stat | SSTICKYORUN
+						| SSTICKYERR, NULL, 0);
 			if (retval != ERROR_OK)
 				return retval;
-
-			retval = dap_queue_ap_read(swjdp,
-					AP_REG_TAR, &mem_ap_tar);
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
 			if (retval != ERROR_OK)
 				return retval;
-
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
+			retval = jtag_execute_queue();
+			if (retval != ERROR_OK)
 				return retval;
-			LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
-					PRIx32, mem_ap_csw, mem_ap_tar);
 
+			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 		}
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
 			return retval;
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
@@ -323,93 +311,65 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 
 /*--------------------------------------------------------------------------*/
 
-static int jtag_idcode_q_read(struct adiv5_dap *dap,
-		uint8_t *ack, uint32_t *data)
-{
-	struct arm_jtag *jtag_info = dap->jtag_info;
-	int retval;
-	struct scan_field fields[1];
-
-	/* This is a standard JTAG operation -- no DAP tweakage */
-	jtag_set_end_state(TAP_IDLE);
-	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
-	if (retval != ERROR_OK)
-		return retval;
-
-	fields[0].num_bits = 32;
-	fields[0].out_value = NULL;
-	fields[0].in_value = (void *) data;
-
-	jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
-	retval = jtag_get_error();
-	if (retval != ERROR_OK)
-		return retval;
-
-	jtag_add_callback(arm_le_to_h_u32,
-			(jtag_callback_data_t) data);
-
-	return retval;
-}
-
 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
 		uint32_t *data)
 {
 	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
-			reg, DPAP_READ, 0, data);
+			reg, DPAP_READ, 0, data, 0);
 }
 
 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 		uint32_t data)
 {
 	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
-			reg, DPAP_WRITE, data, NULL);
+			reg, DPAP_WRITE, data, NULL, 0);
 }
 
 /** Select the AP register bank matching bits 7:4 of reg. */
-static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
+static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
 {
-	uint32_t select = reg & 0x000000F0;
+	struct adiv5_dap *dap = ap->dap;
+	uint32_t select = ((uint32_t)ap->ap_num << 24) | (reg & 0x000000F0);
 
-	if (select == dap->ap_bank_value)
+	if (select == dap->select)
 		return ERROR_OK;
-	dap->ap_bank_value = select;
 
-	select |= dap->apsel;
+	dap->select = select;
 
 	return jtag_dp_q_write(dap, DP_SELECT, select);
 }
 
-static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
+static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
 		uint32_t *data)
 {
-	int retval = jtag_ap_q_bankselect(dap, reg);
+	int retval = jtag_ap_q_bankselect(ap, reg);
 
 	if (retval != ERROR_OK)
 		return retval;
 
-	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
-			DPAP_READ, 0, data);
+	return adi_jtag_scan_inout_check_u32(ap->dap, JTAG_DP_APACC, reg,
+			DPAP_READ, 0, data, ap->memaccess_tck);
 }
 
-static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
+static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
 		uint32_t data)
 {
 	uint8_t out_value_buf[4];
 
-	int retval = jtag_ap_q_bankselect(dap, reg);
+	int retval = jtag_ap_q_bankselect(ap, reg);
 	if (retval != ERROR_OK)
 		return retval;
 
 	buf_set_u32(out_value_buf, 0, 32, data);
 
-	return adi_jtag_ap_write_check(dap, reg, out_value_buf);
+	return adi_jtag_ap_write_check(ap, reg, out_value_buf);
 }
 
 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
 {
 	/* for JTAG, this is the only valid ABORT register operation */
 	return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
-			0, DPAP_WRITE, 1, NULL, ack);
+			0, DPAP_WRITE, 1, NULL, ack, 0);
 }
 
 static int jtag_dp_run(struct adiv5_dap *dap)
@@ -421,17 +381,16 @@ static int jtag_dp_run(struct adiv5_dap *dap)
  * part of DAP setup
 */
 const struct dap_ops jtag_dp_ops = {
-	.queue_idcode_read =	jtag_idcode_q_read,
-	.queue_dp_read =	jtag_dp_q_read,
-	.queue_dp_write =	jtag_dp_q_write,
-	.queue_ap_read =	jtag_ap_q_read,
-	.queue_ap_write =	jtag_ap_q_write,
-	.queue_ap_abort =	jtag_ap_q_abort,
-	.run =			jtag_dp_run,
+	.queue_dp_read       = jtag_dp_q_read,
+	.queue_dp_write      = jtag_dp_q_write,
+	.queue_ap_read       = jtag_ap_q_read,
+	.queue_ap_write      = jtag_ap_q_write,
+	.queue_ap_abort      = jtag_ap_q_abort,
+	.run                 = jtag_dp_run,
 };
 
 
-const uint8_t swd2jtag_bitseq[] = {
+static const uint8_t swd2jtag_bitseq[] = {
 	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 	 * putting both JTAG and SWD logic into reset state.
 	 */