X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Fadi_v5_jtag.c;h=75461c3fa7e8bf95fd627e8914bf4136d56c6a92;hp=d59465bee04e7509e390465efeaedb89785e2657;hb=b48d1f66378fac886d5bc32d7302da48c89d8a75;hpb=fc9de56a251a7cfc2610cc1904a69fc7b9fd3011

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index d59465bee0..75461c3fa7 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -86,9 +86,11 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
 	struct arm_jtag *jtag_info = dap->jtag_info;
 	struct scan_field fields[2];
 	uint8_t out_addr_buf;
+	int retval;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* Scan out a read or write operation using some DP or AP register.
 	 * For APACC access with any sticky error flag set, this is discarded.
@@ -121,7 +123,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
 		jtag_add_runtest(dap->memaccess_tck,
 				TAP_IDLE);
 
-	return jtag_get_error();
+	return ERROR_OK;
 }
 
 /**
@@ -189,28 +191,38 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 
 	/* too expensive to call keep_alive() here */
 
-#if 0
-	/* Danger!!!! BROKEN!!!! */
-	adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
-			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-	/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
-	R956 introduced the check on return value here and now Michael Schwingen reports
-	that this code no longer works....
-
-	https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
-	*/
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("BUG: Why does this fail the first time????");
-	}
-	/* Why??? second time it works??? */
-#endif
+	/* Here be dragons!
+	 *
+	 * It is easy to be in a JTAG clock range where the target
+	 * is not operating in a stable fashion. This happens
+	 * for a few reasons:
+	 *
+	 * - the user may construct a simple test case to try to see
+	 * if a higher JTAG clock works to eke out more performance.
+	 * This simple case may pass, but more complex situations can
+	 * fail.
+	 *
+	 * - The mostly works JTAG clock rate and the complete failure
+	 * JTAG clock rate may be as much as 2-4x apart. This seems
+	 * to be especially true on RC oscillator driven parts.
+	 *
+	 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
+	 * times here seems to "make things better here", it is just
+	 * hiding problems with too high a JTAG clock.
+	 *
+	 * Note that even if some parts have RCLK/RTCK, that doesn't
+	 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
+	 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
+	 * before the RC oscillator phase is not yet complete.
+	 */
 
 	/* Post CTRL/STAT read; discard any previous posted read value
 	 * but collect its ACK status.
 	 */
-	adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+	retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+	if (retval != ERROR_OK)
+		return retval;
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
@@ -244,8 +256,10 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if (retval != ERROR_OK)
+				return retval;
 			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 			dap->ack = dap->ack & 0x7;
@@ -260,7 +274,11 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 		/* Check power to debug regions */
 		if ((ctrlstat & 0xf0000000) != 0xf0000000)
-			 ahbap_debugport_init(dap);
+		{
+			retval = ahbap_debugport_init(dap);
+			if (retval != ERROR_OK)
+				return retval;
+		}
 		else
 		{
 			uint32_t mem_ap_csw, mem_ap_tar;
@@ -286,12 +304,16 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 				LOG_ERROR("JTAG-DP STICKY ERROR");
 
 			/* Clear Sticky Error Bits */
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_WRITE,
 					dap->dp_ctrl_stat | SSTICKYORUN
 						| SSTICKYERR, NULL);
-			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			if (retval != ERROR_OK)
+				return retval;
+			retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if (retval != ERROR_OK)
+				return retval;
 			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 
@@ -331,7 +353,6 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
 	struct scan_field fields[1];
 
 	/* This is a standard JTAG operation -- no DAP tweakage */
-	jtag_set_end_state(TAP_IDLE);
 	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
@@ -341,14 +362,11 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
 	fields[0].in_value = (void *) data;
 
 	jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
-	retval = jtag_get_error();
-	if (retval != ERROR_OK)
-		return retval;
 
 	jtag_add_callback(arm_le_to_h_u32,
 			(jtag_callback_data_t) data);
 
-	return retval;
+	return ERROR_OK;
 }
 
 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
@@ -368,15 +386,15 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 /** Select the AP register bank matching bits 7:4 of reg. */
 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
 {
-	uint32_t select = reg & 0x000000F0;
+	uint32_t select_ap_bank = reg & 0x000000F0;
 
-	if (select == dap->ap_bank_value)
+	if (select_ap_bank == dap->ap_bank_value)
 		return ERROR_OK;
-	dap->ap_bank_value = select;
+	dap->ap_bank_value = select_ap_bank;
 
-	select |= dap->apsel;
+	select_ap_bank |= dap->ap_current;
 
-	return jtag_dp_q_write(dap, DP_SELECT, select);
+	return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
 }
 
 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
@@ -431,7 +449,7 @@ const struct dap_ops jtag_dp_ops = {
 };
 
 
-const uint8_t swd2jtag_bitseq[] = {
+static const uint8_t swd2jtag_bitseq[] = {
 	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
 	 * putting both JTAG and SWD logic into reset state.
 	 */