X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2FMakefile.am;h=2a7cc4b3b335e78beb5237ce6659c894f05f9aa3;hp=c20ac0f03a99b1bca8f0c18dfb51c8025cbddf6e;hb=1fbe8450a9dd99a66f6a4035652beb400deb9277;hpb=a3b9e12aecc3021bc3022eca93d07f7d11255b3b

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index c20ac0f03a..2a7cc4b3b3 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -4,7 +4,9 @@ else
 OOCD_TRACE_FILES =
 endif
 
-%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la
+%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
+	%D%/riscv/libriscv.la
+
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -19,7 +21,9 @@ noinst_LTLIBRARIES += %D%/libtarget.la
 	$(AVR32_SRC) \
 	$(MIPS32_SRC) \
 	$(NDS32_SRC) \
+	$(STM8_SRC) \
 	$(INTEL_IA32_SRC) \
+	$(ESIRISC_SRC) \
 	%D%/avrt.c \
 	%D%/dsp563xx.c \
 	%D%/dsp563xx_once.c \
@@ -28,6 +32,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
 
 if TARGET64
 %C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
+%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
 endif
 
 TARGET_CORE_SRC = \
@@ -38,6 +43,7 @@ TARGET_CORE_SRC = \
 	%D%/target.c \
 	%D%/target_request.c \
 	%D%/testee.c \
+	%D%/semihosting_common.c \
 	%D%/smp.c
 
 ARMV4_5_SRC = \
@@ -70,13 +76,17 @@ ARMV7_SRC = \
 	%D%/armv7m_trace.c \
 	%D%/cortex_m.c \
 	%D%/armv7a.c \
+	%D%/armv7a_mmu.c \
 	%D%/cortex_a.c \
-	%D%/ls1_sap.c
+	%D%/ls1_sap.c \
+	%D%/mem_ap.c
 
 ARMV8_SRC = \
 	%D%/armv8_dpm.c \
+	%D%/armv8_opcodes.c \
 	%D%/aarch64.c \
-	%D%/armv8.c
+	%D%/armv8.c \
+	%D%/armv8_cache.c
 
 ARM_DEBUG_SRC = \
 	%D%/arm_dpm.c \
@@ -85,6 +95,7 @@ ARM_DEBUG_SRC = \
 	%D%/arm_simulator.c \
 	%D%/arm_semihosting.c \
 	%D%/arm_adi_v5.c \
+	%D%/arm_dap.c \
 	%D%/armv7a_cache.c \
 	%D%/armv7a_cache_l2x.c \
 	%D%/adi_v5_jtag.c \
@@ -94,7 +105,8 @@ ARM_DEBUG_SRC = \
 	%D%/etb.c \
 	%D%/etm.c \
 	$(OOCD_TRACE_FILES) \
-	%D%/etm_dummy.c
+	%D%/etm_dummy.c \
+	%D%/arm_cti.c
 
 AVR32_SRC = \
 	%D%/avr32_ap7k.c \
@@ -109,6 +121,13 @@ MIPS32_SRC = \
 	%D%/mips32_dmaacc.c \
 	%D%/mips_ejtag.c
 
+MIPS64_SRC = \
+	%D%/mips64.c \
+	%D%/mips32_pracc.c \
+	%D%/mips64_pracc.c \
+	%D%/trace.c \
+	%D%/mips_ejtag.c
+
 NDS32_SRC = \
 	%D%/nds32.c \
 	%D%/nds32_reg.c \
@@ -121,12 +140,20 @@ NDS32_SRC = \
 	%D%/nds32_v3m.c \
 	%D%/nds32_aice.c
 
+STM8_SRC = \
+	%D%/stm8.c
+
 INTEL_IA32_SRC = \
 	%D%/quark_x10xx.c \
 	%D%/quark_d20xx.c \
 	%D%/lakemont.c \
 	%D%/x86_32_common.c
 
+ESIRISC_SRC = \
+	%D%/esirisc.c \
+	%D%/esirisc_jtag.c \
+	%D%/esirisc_trace.c
+
 %C%_libtarget_la_SOURCES += \
 	%D%/algorithm.h \
 	%D%/arm.h \
@@ -135,6 +162,7 @@ INTEL_IA32_SRC = \
 	%D%/arm_adi_v5.h \
 	%D%/armv7a_cache.h \
 	%D%/armv7a_cache_l2x.h \
+	%D%/armv7a_mmu.h \
 	%D%/arm_disassembler.h \
 	%D%/arm_opcodes.h \
 	%D%/arm_simulator.h \
@@ -158,6 +186,7 @@ INTEL_IA32_SRC = \
 	%D%/armv8.h \
 	%D%/armv8_dpm.h \
 	%D%/armv8_opcodes.h \
+	%D%/armv8_cache.h \
 	%D%/avrt.h \
 	%D%/dsp563xx.h \
 	%D%/dsp563xx_once.h \
@@ -172,10 +201,12 @@ INTEL_IA32_SRC = \
 	%D%/etm_dummy.h \
 	%D%/image.h \
 	%D%/mips32.h \
+	%D%/mips64.h \
 	%D%/mips_m4k.h \
 	%D%/mips_ejtag.h \
 	%D%/mips32_pracc.h \
 	%D%/mips32_dmaacc.h \
+	%D%/mips64_pracc.h \
 	%D%/oocd_trace.h \
 	%D%/register.h \
 	%D%/target.h \
@@ -201,7 +232,15 @@ INTEL_IA32_SRC = \
 	%D%/nds32_v3.h \
 	%D%/nds32_v3m.h \
 	%D%/nds32_aice.h \
+	%D%/semihosting_common.h \
+	%D%/stm8.h \
 	%D%/lakemont.h \
-	%D%/x86_32_common.h
+	%D%/x86_32_common.h \
+	%D%/arm_cti.h \
+	%D%/esirisc.h \
+	%D%/esirisc_jtag.h \
+	%D%/esirisc_regs.h \
+	%D%/esirisc_trace.h
 
 include %D%/openrisc/Makefile.am
+include %D%/riscv/Makefile.am