X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fjtag%2Fbitbang.c;h=e8d082a7aa0b3f4d2fdca2420e4e37336a29d777;hp=a4e415c2ec8cff69c5de240ddffe67575bb629d9;hb=526fe3d83e118d87af34353a7140c02f3f1a3c19;hpb=4411c2643e41d023a1909b1040361912422be6c0

diff --git a/src/jtag/bitbang.c b/src/jtag/bitbang.c
index a4e415c2ec..e8d082a7aa 100644
--- a/src/jtag/bitbang.c
+++ b/src/jtag/bitbang.c
@@ -2,6 +2,9 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                      *
+ *   oyvind.harboe@zylin.com                                               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -34,16 +37,33 @@
 #include <stdlib.h>
 #include <unistd.h>
 
-#include <sys/time.h>
-#include <time.h>
-
 bitbang_interface_t *bitbang_interface;
 
+
+/* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
+ * 
+ * Set this to 1 and str912 reset halt will fail.
+ * 
+ * If someone can submit a patch with an explanation it will be greatly
+ * appreciated, but as far as I can tell (ØH) DCLK is generated upon
+ * clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
+ * The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI 
+ * state". With hardware there is no such thing as *while* in a state. There
+ * are only edges. So clk => 0 is in fact a very subtle state transition that
+ * happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
+ * 
+ * For "reset halt" the last thing that happens before srst is asserted
+ * is that the breakpoint is set up. If DCLK is not wiggled one last
+ * time before the reset, then the breakpoint is not set up and
+ * "reset halt" will fail to halt.
+ * 
+ */
+#define CLOCK_IDLE() 0 
+
 int bitbang_execute_queue(void);
 
 /* The bitbang driver leaves the TCK 0 when in idle */
 
-
 void bitbang_end_state(enum tap_state state)
 {
 	if (tap_move_map[state] != -1)
@@ -66,7 +86,7 @@ void bitbang_state_move(void) {
 		bitbang_interface->write(0, tms, 0);
 		bitbang_interface->write(1, tms, 0);
 	}
-	bitbang_interface->write(0, tms, 0);
+	bitbang_interface->write(CLOCK_IDLE(), tms, 0);
 	
 	cur_state = end_state;
 }
@@ -102,7 +122,7 @@ void bitbang_path_move(pathmove_command_t *cmd)
 		num_states--;
 	}
 	
-	bitbang_interface->write(0, tms, 0);
+	bitbang_interface->write(CLOCK_IDLE(), tms, 0);
 
 	end_state = cur_state;
 }
@@ -121,12 +141,12 @@ void bitbang_runtest(int num_cycles)
 	}
 	
 	/* execute num_cycles */
-	bitbang_interface->write(0, 0, 0);
 	for (i = 0; i < num_cycles; i++)
 	{
-		bitbang_interface->write(1, 0, 0);
 		bitbang_interface->write(0, 0, 0);
+		bitbang_interface->write(1, 0, 0);
 	}
+	bitbang_interface->write(CLOCK_IDLE(), 0, 0);
 	
 	/* finish in end_state */
 	bitbang_end_state(saved_end_state);
@@ -191,7 +211,7 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
 	 */
 	bitbang_interface->write(0, 0, 0);
 	bitbang_interface->write(1, 0, 0);
-	bitbang_interface->write(0, 0, 0);
+	bitbang_interface->write(CLOCK_IDLE(), 0, 0);
 	
 	if (ir_scan)
 		cur_state = TAP_PI;
@@ -239,7 +259,7 @@ int bitbang_execute_queue(void)
 #ifdef _DEBUG_JTAG_IO_
 				LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
 #endif
-				if (cmd->cmd.reset->trst == 1)
+				if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
 				{
 					cur_state = TAP_TLR;
 				}