X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fs3c2412_nand.c;h=1ddcff04eab2bb9d1c74f69baf6700e33f0f1b1c;hp=6137d0d146a63b277cc4b266c060b7904c7af888;hb=d17e1cd93384d56886be7e67cf2b31e97118d811;hpb=f76cf27380af20a6e1d46448c146140234d914f9

diff --git a/src/flash/s3c2412_nand.c b/src/flash/s3c2412_nand.c
index 6137d0d146..1ddcff04ea 100644
--- a/src/flash/s3c2412_nand.c
+++ b/src/flash/s3c2412_nand.c
@@ -1,86 +1,86 @@
-/* src/flash/s3c2412_nand.c
- *
- * S3C2412 OpenOCD NAND Flash controller support.
- *
- * Copyright 2007,2008 Ben Dooks <ben@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * Many thanks to Simtec Electronics for sponsoring this work.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-#include "log.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-#include "nand.h"
-#include "s3c24xx_nand.h"
-#include "target.h"
-
-int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
-int s3c2412_init(struct nand_device_s *device);
-
-nand_flash_controller_t s3c2412_nand_controller =
-{
-	.name			= "s3c2412",
-	.nand_device_command	= s3c2412_nand_device_command,
-	.register_commands	= s3c24xx_register_commands,
-	.init			= s3c2412_init,
-	.reset			= s3c24xx_reset,
-	.command		= s3c24xx_command,
-	.address		= s3c24xx_address,
-	.write_data		= s3c24xx_write_data,
-	.read_data		= s3c24xx_read_data,
-	.write_page		= s3c24xx_write_page,
-	.read_page		= s3c24xx_read_page,
-	.write_block_data	= s3c2440_write_block_data,
-	.read_block_data	= s3c2440_read_block_data,
-	.controller_ready	= s3c24xx_controller_ready,
-	.nand_ready		= s3c2440_nand_ready,
-};
-
-int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
-				char **args, int argc,
-				struct nand_device_s *device)
-{
-	s3c24xx_nand_controller_t *info;
-
-	info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
-	if (info == NULL) {
-		return ERROR_NAND_DEVICE_INVALID;
-	}
-
-	/* fill in the address fields for the core device */
-	info->cmd = S3C2440_NFCMD;
-	info->addr = S3C2440_NFADDR;
-	info->data = S3C2440_NFDATA;
-	info->nfstat = S3C2412_NFSTAT;
-	
-	return ERROR_OK;
-}
-
-int s3c2412_init(struct nand_device_s *device)
-{
-	s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
-	target_t *target = s3c24xx_info->target;
-
-	target_write_u32(target, S3C2410_NFCONF,
-			 S3C2440_NFCONF_TACLS(3) |
-			 S3C2440_NFCONF_TWRPH0(7) |
-			 S3C2440_NFCONF_TWRPH1(7));
-
-	target_write_u32(target, S3C2440_NFCONT,
-			 S3C2412_NFCONT_INIT_MAIN_ECC |
-			 S3C2440_NFCONT_ENABLE);
-
-	return ERROR_OK;
-}
+/* src/flash/s3c2412_nand.c
+ *
+ * S3C2412 OpenOCD NAND Flash controller support.
+ *
+ * Copyright 2007,2008 Ben Dooks <ben@fluff.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Many thanks to Simtec Electronics for sponsoring this work.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+#include "log.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "nand.h"
+#include "s3c24xx_nand.h"
+#include "target.h"
+
+int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
+int s3c2412_init(struct nand_device_s *device);
+
+nand_flash_controller_t s3c2412_nand_controller =
+{
+	.name			= "s3c2412",
+	.nand_device_command	= s3c2412_nand_device_command,
+	.register_commands	= s3c24xx_register_commands,
+	.init			= s3c2412_init,
+	.reset			= s3c24xx_reset,
+	.command		= s3c24xx_command,
+	.address		= s3c24xx_address,
+	.write_data		= s3c24xx_write_data,
+	.read_data		= s3c24xx_read_data,
+	.write_page		= s3c24xx_write_page,
+	.read_page		= s3c24xx_read_page,
+	.write_block_data	= s3c2440_write_block_data,
+	.read_block_data	= s3c2440_read_block_data,
+	.controller_ready	= s3c24xx_controller_ready,
+	.nand_ready		= s3c2440_nand_ready,
+};
+
+int s3c2412_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
+				char **args, int argc,
+				struct nand_device_s *device)
+{
+	s3c24xx_nand_controller_t *info;
+
+	info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
+	if (info == NULL) {
+		return ERROR_NAND_DEVICE_INVALID;
+	}
+
+	/* fill in the address fields for the core device */
+	info->cmd = S3C2440_NFCMD;
+	info->addr = S3C2440_NFADDR;
+	info->data = S3C2440_NFDATA;
+	info->nfstat = S3C2412_NFSTAT;
+	
+	return ERROR_OK;
+}
+
+int s3c2412_init(struct nand_device_s *device)
+{
+	s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
+	target_t *target = s3c24xx_info->target;
+
+	target_write_u32(target, S3C2410_NFCONF,
+			 S3C2440_NFCONF_TACLS(3) |
+			 S3C2440_NFCONF_TWRPH0(7) |
+			 S3C2440_NFCONF_TWRPH1(7));
+
+	target_write_u32(target, S3C2440_NFCONT,
+			 S3C2412_NFCONT_INIT_MAIN_ECC |
+			 S3C2440_NFCONT_ENABLE);
+
+	return ERROR_OK;
+}