X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32l4x.c;h=7d1e4298406d0c0b2af50f6d4739d3b456752a77;hp=f71369330eb451d6b5a5788d831e88a7e06c6e0a;hb=a4d50544de07f13e3f9644d2b48e41ebdc91a7a3;hpb=47d0930410bc6f9fdf1d59a60a60fcca4c7bb1d4

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index f71369330e..7d1e429840 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -33,6 +33,9 @@
  * RM0394 (STM32L43x/44x/45x/46x)
  * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
  *
+ * RM0432 (STM32L4R/4Sxx)
+ * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
+ *
  * STM32L476RG Datasheet (for erase timing)
  * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
  *
@@ -43,6 +46,14 @@
  *
  * RM0394 devices have a single bank only.
  *
+ * RM0432 devices have single and dual bank operating modes.
+ * The FLASH size is 1Mbyte or 2Mbyte.
+ * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
+ *
+ * Bank mode is controlled by two different bits in option bytes register.
+ * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
+ * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
+ *
  */
 
 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
@@ -57,8 +68,8 @@
 #define STM32_FLASH_CR      0x40022014
 #define STM32_FLASH_OPTR    0x40022020
 #define STM32_FLASH_WRP1AR  0x4002202c
-#define STM32_FLASH_WRP2AR  0x40022030
-#define STM32_FLASH_WRP1BR  0x4002204c
+#define STM32_FLASH_WRP1BR  0x40022030
+#define STM32_FLASH_WRP2AR  0x4002204c
 #define STM32_FLASH_WRP2BR  0x40022050
 
 /* FLASH_CR register bits */
@@ -70,8 +81,10 @@
 #define FLASH_CR_BKER  (1 << 11)
 #define FLASH_MER2     (1 << 15)
 #define FLASH_STRT     (1 << 16)
+#define FLASH_OPTSTRT  (1 << 17)
 #define FLASH_EOPIE    (1 << 24)
 #define FLASH_ERRIE    (1 << 25)
+#define FLASH_OBLLAUNCH (1 << 27)
 #define FLASH_OPTLOCK  (1 << 30)
 #define FLASH_LOCK     (1 << 31)
 
@@ -80,7 +93,7 @@
 #define FLASH_BSY      (1 << 16)
 /* Fast programming not used => related errors not used*/
 #define FLASH_PGSERR   (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR   (1 << 6) /* Size  error */
+#define FLASH_SIZERR   (1 << 6) /* Size error */
 #define FLASH_PGAERR   (1 << 5) /* Programming alignment error */
 #define FLASH_WRPERR   (1 << 4) /* Write protection error */
 #define FLASH_PROGERR  (1 << 3) /* Programming error */
@@ -91,7 +104,8 @@
 
 /* STM32_FLASH_OBR bit definitions (reading) */
 
-#define OPT_DUALBANK   21	/* dual flash bank only */
+#define OPT_DBANK_LE_1M (1 << 21)	/* dual bank for devices up to 1M flash */
+#define OPT_DBANK_GE_2M (1 << 22)	/* dual bank for devices with 2M flash */
 
 /* register unlock keys */
 
@@ -102,28 +116,17 @@
 #define OPTKEY1        0x08192A3B
 #define OPTKEY2        0x4C5D6E7F
 
+#define RDP_LEVEL_0	   0xAA
+#define RDP_LEVEL_1	   0xBB
+#define RDP_LEVEL_2	   0xCC
+
 
 /* other registers */
 #define DBGMCU_IDCODE	0xE0042000
 #define FLASH_SIZE_REG	0x1FFF75E0
 
-struct stm32l4_options {
-	uint8_t RDP;
-	uint16_t bank_b_start;
-	uint8_t user_options;
-	uint8_t wpr1a_start;
-	uint8_t wpr1a_end;
-	uint8_t wpr1b_start;
-	uint8_t wpr1b_end;
-	uint8_t wpr2a_start;
-	uint8_t wpr2a_end;
-	uint8_t wpr2b_start;
-	uint8_t wpr2b_end;
-    /* Fixme: Handle PCROP */
-};
-
 struct stm32l4_flash_bank {
-	struct stm32l4_options option_bytes;
+	uint16_t bank2_start;
 	int probed;
 };
 
@@ -265,97 +268,80 @@ static int stm32l4_unlock_option_reg(struct target *target)
 	return ERROR_OK;
 }
 
-static int stm32l4_read_options(struct flash_bank *bank)
+static int stm32l4_read_option(struct flash_bank *bank, uint32_t address, uint32_t* value)
 {
-	uint32_t optiondata;
-	struct stm32l4_flash_bank *stm32l4_info = NULL;
 	struct target *target = bank->target;
+	return target_read_u32(target, address, value);
+}
 
-	stm32l4_info = bank->driver_priv;
+static int stm32l4_write_option(struct flash_bank *bank, uint32_t address, uint32_t value, uint32_t mask)
+{
+	struct target *target = bank->target;
+	uint32_t optiondata;
 
-	/* read current option bytes */
-	int retval = target_read_u32(target, STM32_FLASH_OPTR, &optiondata);
+	int retval = target_read_u32(target, address, &optiondata);
 	if (retval != ERROR_OK)
 		return retval;
 
-	stm32l4_info->option_bytes.user_options = (optiondata >> 8) & 0x3ffff;
-	stm32l4_info->option_bytes.RDP = optiondata & 0xff;
-
-	retval = target_read_u32(target, STM32_FLASH_WRP1AR, &optiondata);
+	retval = stm32l4_unlock_reg(target);
 	if (retval != ERROR_OK)
 		return retval;
-	stm32l4_info->option_bytes.wpr1a_start =  optiondata         & 0xff;
-	stm32l4_info->option_bytes.wpr1a_end   = (optiondata >> 16)  & 0xff;
 
-	retval = target_read_u32(target, STM32_FLASH_WRP2AR, &optiondata);
+	retval = stm32l4_unlock_option_reg(target);
 	if (retval != ERROR_OK)
 		return retval;
-	stm32l4_info->option_bytes.wpr2a_start =  optiondata         & 0xff;
-	stm32l4_info->option_bytes.wpr2a_end   = (optiondata >> 16)  & 0xff;
 
-	retval = target_read_u32(target, STM32_FLASH_WRP1BR, &optiondata);
+	optiondata = (optiondata & ~mask) | (value & mask);
+
+	retval = target_write_u32(target, address, optiondata);
 	if (retval != ERROR_OK)
 		return retval;
-	stm32l4_info->option_bytes.wpr1b_start =  optiondata         & 0xff;
-	stm32l4_info->option_bytes.wpr1b_end   = (optiondata >> 16)  & 0xff;
 
-	retval = target_read_u32(target, STM32_FLASH_WRP2BR, &optiondata);
+	retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OPTSTRT);
 	if (retval != ERROR_OK)
 		return retval;
-	stm32l4_info->option_bytes.wpr2b_start =  optiondata         & 0xff;
-	stm32l4_info->option_bytes.wpr2b_end   = (optiondata >> 16)  & 0xff;
-
-	if (stm32l4_info->option_bytes.RDP != 0xAA)
-		LOG_INFO("Device Security Bit Set");
 
-	return ERROR_OK;
-}
-
-static int stm32l4_write_options(struct flash_bank *bank)
-{
-	struct stm32l4_flash_bank *stm32l4_info = NULL;
-	struct target *target = bank->target;
-	uint32_t optiondata;
-
-	stm32l4_info = bank->driver_priv;
-
-	(void) optiondata;
-	(void) stm32l4_info;
-
-	int retval = stm32l4_unlock_option_reg(target);
+	retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 	if (retval != ERROR_OK)
 		return retval;
-	/* FIXME: Implement Option writing!*/
-	return ERROR_OK;
+
+	return retval;
 }
 
 static int stm32l4_protect_check(struct flash_bank *bank)
 {
 	struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
-
-	/* read write protection settings */
-	int retval = stm32l4_read_options(bank);
-	if (retval != ERROR_OK) {
-		LOG_DEBUG("unable to read option bytes");
-		return retval;
-	}
+	uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
+	stm32l4_read_option(bank, STM32_FLASH_WRP1AR, &wrp1ar);
+	stm32l4_read_option(bank, STM32_FLASH_WRP1BR, &wrp1br);
+	stm32l4_read_option(bank, STM32_FLASH_WRP2AR, &wrp2ar);
+	stm32l4_read_option(bank, STM32_FLASH_WRP2BR, &wrp2br);
+
+	const uint8_t wrp1a_start = wrp1ar & 0xFF;
+	const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
+	const uint8_t wrp1b_start = wrp1br & 0xFF;
+	const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
+	const uint8_t wrp2a_start = wrp2ar & 0xFF;
+	const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
+	const uint8_t wrp2b_start = wrp2br & 0xFF;
+	const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
 
 	for (int i = 0; i < bank->num_sectors; i++) {
-		if (i < stm32l4_info->option_bytes.bank_b_start) {
-			if (((i >= stm32l4_info->option_bytes.wpr1a_start) &&
-				 (i <= stm32l4_info->option_bytes.wpr1a_end)) ||
-				((i >= stm32l4_info->option_bytes.wpr2a_start) &&
-				 (i <= stm32l4_info->option_bytes.wpr2a_end)))
+		if (i < stm32l4_info->bank2_start) {
+			if (((i >= wrp1a_start) &&
+				 (i <= wrp1a_end)) ||
+				((i >= wrp1b_start) &&
+				 (i <= wrp1b_end)))
 				bank->sectors[i].is_protected = 1;
 			else
 				bank->sectors[i].is_protected = 0;
 		} else {
 			uint8_t snb;
-			snb = i - stm32l4_info->option_bytes.bank_b_start + 256;
-			if (((snb >= stm32l4_info->option_bytes.wpr1b_start) &&
-				 (snb <= stm32l4_info->option_bytes.wpr1b_end)) ||
-				((snb >= stm32l4_info->option_bytes.wpr2b_start) &&
-				 (snb <= stm32l4_info->option_bytes.wpr2b_end)))
+			snb = i - stm32l4_info->bank2_start;
+			if (((snb >= wrp2a_start) &&
+				 (snb <= wrp2a_end)) ||
+				((snb >= wrp2b_start) &&
+				 (snb <= wrp2b_end)))
 				bank->sectors[i].is_protected = 1;
 			else
 				bank->sectors[i].is_protected = 0;
@@ -388,7 +374,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 	1. Check that no Flash memory operation is ongoing by
        checking the BSY bit in the FLASH_SR register
 	2. Set the PER bit and select the page and bank
-	   you wish to erase  in the FLASH_CR register
+	   you wish to erase in the FLASH_CR register
 	3. Set the STRT bit in the FLASH_CR register
 	4. Wait for the BSY bit to be cleared
 	 */
@@ -398,9 +384,9 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last)
 		uint32_t erase_flags;
 		erase_flags = FLASH_PER | FLASH_STRT;
 
-		if  (i >= stm32l4_info->option_bytes.bank_b_start) {
+		if (i >= stm32l4_info->bank2_start) {
 			uint8_t snb;
-			snb = (i - stm32l4_info->option_bytes.bank_b_start) + 256;
+			snb = i - stm32l4_info->bank2_start;
 			erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
 		} else
 			erase_flags |= i << FLASH_PAGE_SHIFT;
@@ -434,20 +420,29 @@ static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	/* read protection settings */
-	int retval = stm32l4_read_options(bank);
-	if (retval != ERROR_OK) {
-		LOG_DEBUG("unable to read option bytes");
-		return retval;
+	int ret = ERROR_OK;
+	/* Bank 2 */
+	uint32_t reg_value = 0xFF; /* Default to bank un-protected */
+	if (last >= stm32l4_info->bank2_start) {
+		if (set == 1) {
+			uint8_t begin = first > stm32l4_info->bank2_start ? first : 0x00;
+			reg_value = ((last & 0xFF) << 16) | begin;
+		}
+
+		ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
 	}
+	/* Bank 1 */
+	reg_value = 0xFF; /* Default to bank un-protected */
+	if (first < stm32l4_info->bank2_start) {
+		if (set == 1) {
+			uint8_t end = last >= stm32l4_info->bank2_start ? 0xFF : last;
+			reg_value = (end << 16) | (first & 0xFF);
+		}
 
-	(void)stm32l4_info;
-	/* FIXME: Write First and last in a valid WRPxx_start/end combo*/
-	retval = stm32l4_write_options(bank);
-	if (retval != ERROR_OK)
-		return retval;
+		ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
+	}
 
-	return ERROR_OK;
+	return ret;
 }
 
 /* Count is in halfwords */
@@ -476,8 +471,10 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	retval = target_write_buffer(target, write_algorithm->address,
 			sizeof(stm32l4_flash_write_code),
 			stm32l4_flash_write_code);
-	if (retval != ERROR_OK)
+	if (retval != ERROR_OK) {
+		target_free_working_area(target, write_algorithm);
 		return retval;
+	}
 
 	/* memory buffer */
 	while (target_alloc_working_area_try(target, buffer_size, &source) !=
@@ -488,7 +485,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
 			 * buffer, free the algorithm */
 			target_free_working_area(target, write_algorithm);
 
-			LOG_WARNING("no large enough working area available, can't do block memory writes");
+			LOG_WARNING("large enough working area not available, can't do block memory writes");
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
 	}
@@ -609,6 +606,9 @@ static int stm32l4_probe(struct flash_bank *bank)
 
 	/* set max flash size depending on family */
 	switch (device_id & 0xfff) {
+	case 0x470:
+		max_flash_size_in_kb = 2048;
+		break;
 	case 0x461:
 	case 0x415:
 		max_flash_size_in_kb = 1024;
@@ -620,7 +620,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 		max_flash_size_in_kb = 256;
 		break;
 	default:
-		LOG_WARNING("Cannot identify target as a STM32L4 family.");
+		LOG_WARNING("Cannot identify target as an STM32L4 family device.");
 		return ERROR_FAIL;
 	}
 
@@ -637,45 +637,88 @@ static int stm32l4_probe(struct flash_bank *bank)
 
 	LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
 
-	/* did we assign flash size? */
-	assert(flash_size_in_kb != 0xffff);
+	/* did we assign a flash size? */
+	assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
 
-	/* get options to for DUAL BANK. */
+	/* get options for DUAL BANK. */
 	retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
 
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* only devices with < 1024 kiB may be set to single bank dual banks */
-	if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
-		stm32l4_info->option_bytes.bank_b_start = 256;
-	else
-		stm32l4_info->option_bytes.bank_b_start = flash_size_in_kb << 9;
+	int num_pages = 0;
+	int page_size = 0;
 
-	/* did we assign flash size? */
-	assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
-
-	/* calculate numbers of pages */
-	int num_pages = flash_size_in_kb / 2;
-
-	/* check that calculation result makes sense */
-	assert(num_pages > 0);
+	switch (device_id & 0xfff) {
+		case 0x470:
+			/* L4R/S have 1M or 2M FLASH and dual/single bank mode.
+			 * Page size is 4K or 8K.*/
+			if (flash_size_in_kb == 2048) {
+				stm32l4_info->bank2_start = 256;
+				if (options & OPT_DBANK_GE_2M) {
+					page_size = 4096;
+					num_pages = 512;
+				} else {
+					page_size = 8192;
+					num_pages = 256;
+				}
+				break;
+			}
+			if (flash_size_in_kb == 1024) {
+				stm32l4_info->bank2_start = 128;
+				if (options & OPT_DBANK_LE_1M) {
+					page_size = 4096;
+					num_pages = 256;
+				} else {
+					page_size = 8192;
+					num_pages = 128;
+				}
+				break;
+			}
+			/* Invalid FLASH size for this device. */
+			LOG_WARNING("Invalid flash size for STM32L4+ family device.");
+			return ERROR_FAIL;
+		case 0x461:
+		case 0x415:
+			/* These are dual-bank devices, we need to check the OPT_DBANK_LE_1M bit here */
+			page_size = 2048;
+			num_pages = flash_size_in_kb / 2;
+			/* check that calculation result makes sense */
+			assert(num_pages > 0);
+			if ((flash_size_in_kb == 1024) || !(options & OPT_DBANK_LE_1M))
+				stm32l4_info->bank2_start = 256;
+			else
+				stm32l4_info->bank2_start = num_pages / 2;
+			break;
+		case 0x462:
+		case 0x435:
+		default:
+			/* These are single-bank devices */
+			page_size = 2048;
+			num_pages = flash_size_in_kb / 2;
+			/* check that calculation result makes sense */
+			assert(num_pages > 0);
+			stm32l4_info->bank2_start = UINT16_MAX;
+			break;
+	}
 
+	/* Release sector table if allocated. */
 	if (bank->sectors) {
 		free(bank->sectors);
 		bank->sectors = NULL;
 	}
 
+	/* Set bank configuration and construct sector table. */
 	bank->base = base_address;
-	bank->size = num_pages * (1 << 11);
+	bank->size = num_pages * page_size;
 	bank->num_sectors = num_pages;
 	bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 	if (!bank->sectors)
 		return ERROR_FAIL; /* Checkme: What better error to use?*/
 
 	for (i = 0; i < num_pages; i++) {
-		bank->sectors[i].offset = i << 11;
-		bank->sectors[i].size = 1 << 11;
+		bank->sectors[i].offset = i * page_size;
+		bank->sectors[i].size = page_size;
 		bank->sectors[i].is_erased = -1;
 		bank->sectors[i].is_protected = 1;
 	}
@@ -718,6 +761,10 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
 	const char *device_str;
 
 	switch (device_id) {
+	case 0x470:
+		device_str = "STM32L4R/4Sxx";
+		break;
+
 	case 0x461:
 		device_str = "STM32L496/4A6";
 		break;
@@ -745,89 +792,6 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
 	return ERROR_OK;
 }
 
-COMMAND_HANDLER(stm32l4_handle_lock_command)
-{
-	struct target *target = NULL;
-	struct stm32l4_flash_bank *stm32l4_info = NULL;
-
-	if (CMD_ARGC < 1)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
-	if (ERROR_OK != retval)
-		return retval;
-
-	stm32l4_info = bank->driver_priv;
-	target = bank->target;
-
-	if (target->state != TARGET_HALTED) {
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (stm32l4_read_options(bank) != ERROR_OK) {
-		command_print(CMD_CTX, "%s failed to read options",
-					  bank->driver->name);
-		return ERROR_OK;
-	}
-
-	/* set readout protection */
-	stm32l4_info->option_bytes.RDP = 0;
-
-	if (stm32l4_write_options(bank) != ERROR_OK) {
-		command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
-		return ERROR_OK;
-	}
-
-	command_print(CMD_CTX, "%s locked", bank->driver->name);
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(stm32l4_handle_unlock_command)
-{
-	struct target *target = NULL;
-	struct stm32l4_flash_bank *stm32l4_info = NULL;
-
-	if (CMD_ARGC < 1)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
-	if (ERROR_OK != retval)
-		return retval;
-
-	stm32l4_info = bank->driver_priv;
-	target = bank->target;
-
-	if (target->state != TARGET_HALTED) {
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (stm32l4_read_options(bank) != ERROR_OK) {
-		command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
-		return ERROR_OK;
-	}
-
-	/* clear readout protection and complementary option bytes
-	 * this will also force a device unlock if set */
-	stm32l4_info->option_bytes.RDP = 0xAA;
-
-	if (stm32l4_write_options(bank) != ERROR_OK) {
-		command_print(CMD_CTX, "%s failed to unlock device",
-					  bank->driver->name);
-		return ERROR_OK;
-	}
-
-	command_print(CMD_CTX, "%s unlocked.\n"
-			"INFO: a reset or power cycle is required "
-			"for the new settings to take effect.", bank->driver->name);
-
-	return ERROR_OK;
-}
-
 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
 {
 	int retval;
@@ -871,7 +835,7 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
 	uint32_t action;
 
 	if (CMD_ARGC < 1) {
-		command_print(CMD_CTX, "stm32x mass_erase <STM32L4 bank>");
+		command_print(CMD_CTX, "stm32l4x mass_erase <STM32L4 bank>");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -887,14 +851,151 @@ COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
 		for (i = 0; i < bank->num_sectors; i++)
 			bank->sectors[i].is_erased = 1;
 
-		command_print(CMD_CTX, "stm32x mass erase complete");
+		command_print(CMD_CTX, "stm32l4x mass erase complete");
 	} else {
-		command_print(CMD_CTX, "stm32x mass erase failed");
+		command_print(CMD_CTX, "stm32l4x mass erase failed");
 	}
 
 	return retval;
 }
 
+COMMAND_HANDLER(stm32l4_handle_option_read_command)
+{
+	if (CMD_ARGC < 2) {
+		command_print(CMD_CTX, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	uint32_t reg_addr = STM32_FLASH_BASE;
+	uint32_t value = 0;
+
+	reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
+
+	retval = stm32l4_read_option(bank, reg_addr, &value);
+	if (ERROR_OK != retval)
+		return retval;
+
+	command_print(CMD_CTX, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
+
+	return retval;
+}
+
+COMMAND_HANDLER(stm32l4_handle_option_write_command)
+{
+	if (CMD_ARGC < 3) {
+		command_print(CMD_CTX, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	uint32_t reg_addr = STM32_FLASH_BASE;
+	uint32_t value = 0;
+	uint32_t mask = 0xFFFFFFFF;
+
+	reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
+	value = strtoul(CMD_ARGV[2], NULL, 16);
+	if (CMD_ARGC > 3)
+		mask = strtoul(CMD_ARGV[3], NULL, 16);
+
+	command_print(CMD_CTX, "%s Option written.\n"
+				"INFO: a reset or power cycle is required "
+				"for the new settings to take effect.", bank->driver->name);
+
+	retval = stm32l4_write_option(bank, reg_addr, value, mask);
+	return retval;
+}
+
+COMMAND_HANDLER(stm32l4_handle_option_load_command)
+{
+	if (CMD_ARGC < 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	struct target *target = bank->target;
+
+	retval = stm32l4_unlock_reg(target);
+	if (ERROR_OK != retval)
+		return retval;
+
+	retval = stm32l4_unlock_option_reg(target);
+	if (ERROR_OK != retval)
+		return retval;
+
+	/* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
+	retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBLLAUNCH);
+
+	command_print(CMD_CTX, "stm32l4x option load (POR) completed.");
+	return retval;
+}
+
+COMMAND_HANDLER(stm32l4_handle_lock_command)
+{
+	struct target *target = NULL;
+
+	if (CMD_ARGC < 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* set readout protection level 1 by erasing the RDP option byte */
+	if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
+		command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
+		return ERROR_OK;
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32l4_handle_unlock_command)
+{
+	struct target *target = NULL;
+
+	if (CMD_ARGC < 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
+		command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
+		return ERROR_OK;
+	}
+
+	return ERROR_OK;
+}
+
 static const struct command_registration stm32l4_exec_command_handlers[] = {
 	{
 		.name = "lock",
@@ -917,6 +1018,27 @@ static const struct command_registration stm32l4_exec_command_handlers[] = {
 		.usage = "bank_id",
 		.help = "Erase entire flash device.",
 	},
+	{
+		.name = "option_read",
+		.handler = stm32l4_handle_option_read_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id reg_offset",
+		.help = "Read & Display device option bytes.",
+	},
+	{
+		.name = "option_write",
+		.handler = stm32l4_handle_option_write_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id reg_offset value mask",
+		.help = "Write device option bit fields with provided value.",
+	},
+	{
+		.name = "option_load",
+		.handler = stm32l4_handle_option_load_command,
+		.mode = COMMAND_EXEC,
+		.usage = "bank_id",
+		.help = "Force re-load of device options (will cause device reset).",
+	},
 	COMMAND_REGISTRATION_DONE
 };