X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f2x.c;h=0e4abb533c6ff672f50a20d752e64be57c957120;hp=a7aba2b3bd98190d1b13cb0a08b46b89d836a9b9;hb=7719e9618e753ac41a46a2488dfba549ac578891;hpb=f9b673322ce0958d530066434a2d21ea1c1710de
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index a7aba2b3bd..0e4abb533c 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -19,9 +19,7 @@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see . *
***************************************************************************/
#ifdef HAVE_CONFIG_H
@@ -59,21 +57,52 @@
* To reduce testing complexity and dangers of regressions,
* a seperate file is used for stm32fx2x.
*
- * 1mByte part with 4 x 16, 1 x 64, 7 x 128kBytes sectors
+ * Sector sizes in kiBytes:
+ * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
+ * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
+ * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
+ * 1 MiByte STM32F42x/43x part with DB1M Option set:
+ * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
*
- * What's the protection page size???
+ * STM32F7[2|3]
+ * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
+ *
+ * STM32F7[4|5]
+ * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
+ *
+ * STM32F7[6|7]
+ * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
+ * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
+ * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
+ * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
+ *
+ * Protection size is sector size.
*
* Tested with STM3220F-EVAL board.
*
- * STM32F21xx series for reference.
+ * STM32F4xx series for reference.
*
- * RM0033
- * http://www.st.com/internet/mcu/product/250192.jsp
+ * RM0090
+ * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
*
* PM0059
* www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
* PROGRAMMING_MANUAL/CD00233952.pdf
*
+ * STM32F7xx series for reference.
+ *
+ * RM0385
+ * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
+ *
+ * RM0410
+ * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
+ *
+ * RM0430
+ * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
+ *
+ * RM0431
+ * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
+ *
* STM32F1x series - notice that this code was copy, pasted and knocked
* into a stm32f2x driver, so in case something has been converted or
* bugs haven't been fixed, here are the original manuals:
@@ -91,6 +120,9 @@
#define FLASH_ERASE_TIMEOUT 10000
#define FLASH_WRITE_TIMEOUT 5
+/* Mass erase time can be as high as 32 s in x8 mode. */
+#define FLASH_MASS_ERASE_TIMEOUT 33000
+
#define STM32_FLASH_BASE 0x40023c00
#define STM32_FLASH_ACR 0x40023c00
#define STM32_FLASH_KEYR 0x40023c04
@@ -99,13 +131,13 @@
#define STM32_FLASH_CR 0x40023c10
#define STM32_FLASH_OPTCR 0x40023c14
#define STM32_FLASH_OPTCR1 0x40023c18
+#define STM32_FLASH_OPTCR2 0x40023c1c
/* FLASH_CR register bits */
-
#define FLASH_PG (1 << 0)
#define FLASH_SER (1 << 1)
-#define FLASH_MER (1 << 2)
-#define FLASH_MER1 (1 << 15)
+#define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
+#define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
#define FLASH_STRT (1 << 16)
#define FLASH_PSIZE_8 (0 << 8)
#define FLASH_PSIZE_16 (1 << 8)
@@ -117,7 +149,6 @@
#define FLASH_LOCK (1 << 31)
/* FLASH_SR register bits */
-
#define FLASH_BSY (1 << 16)
#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
#define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
@@ -128,21 +159,16 @@
#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
/* STM32_FLASH_OPTCR register bits */
+#define OPTCR_LOCK (1 << 0)
+#define OPTCR_START (1 << 1)
+#define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
+#define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
+#define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
-#define OPT_LOCK (1 << 0)
-#define OPT_START (1 << 1)
-
-/* STM32_FLASH_OBR bit definitions (reading) */
-
-#define OPT_ERROR 0
-#define OPT_READOUT 1
-#define OPT_RDWDGSW 2
-#define OPT_RDRSTSTOP 3
-#define OPT_RDRSTSTDBY 4
-#define OPT_BFB2 5 /* dual flash bank only */
+/* STM32_FLASH_OPTCR2 register bits */
+#define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
/* register unlock keys */
-
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
@@ -152,14 +178,20 @@
struct stm32x_options {
uint8_t RDP;
- uint8_t user_options;
+ uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
uint32_t protection;
+ uint32_t boot_addr;
+ uint32_t optcr2_pcrop;
};
struct stm32x_flash_bank {
struct stm32x_options option_bytes;
int probed;
- bool has_large_mem; /* stm32f42x/stm32f43x family */
+ bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
+ bool has_extra_options; /* F42x/43x/469/479/7xx */
+ bool has_boot_addr; /* F7xx */
+ bool has_optcr2_pcrop; /* F72x/73x */
+ int protection_bits; /* F413/423 */
uint32_t user_bank_size;
};
@@ -258,7 +290,7 @@ static int stm32x_unlock_reg(struct target *target)
return retval;
if (ctrl & FLASH_LOCK) {
- LOG_ERROR("flash not unlocked STM32_FLASH_CR: %x", ctrl);
+ LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -273,7 +305,7 @@ static int stm32x_unlock_option_reg(struct target *target)
if (retval != ERROR_OK)
return retval;
- if ((ctrl & OPT_LOCK) == 0)
+ if ((ctrl & OPTCR_LOCK) == 0)
return ERROR_OK;
/* unlock option registers */
@@ -289,8 +321,8 @@ static int stm32x_unlock_option_reg(struct target *target)
if (retval != ERROR_OK)
return retval;
- if (ctrl & OPT_LOCK) {
- LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %x", ctrl);
+ if (ctrl & OPTCR_LOCK) {
+ LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -310,18 +342,46 @@ static int stm32x_read_options(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- stm32x_info->option_bytes.user_options = optiondata & 0xec;
+ /* caution: F2 implements 5 bits (WDG_SW only)
+ * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
+ stm32x_info->option_bytes.user_options = optiondata & 0xfc;
stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
- stm32x_info->option_bytes.protection = (optiondata >> 16) & 0xfff;
+ stm32x_info->option_bytes.protection =
+ (optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
- if (stm32x_info->has_large_mem) {
+ if (stm32x_info->has_extra_options) {
+ /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
+ stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
+ ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
+ }
+ if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
if (retval != ERROR_OK)
return retval;
- /* append protection bits */
- stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
+ /* FLASH_OPTCR1 has quite diffent meanings ... */
+ if (stm32x_info->has_boot_addr) {
+ /* for F7xx it contains boot0 and boot1 */
+ stm32x_info->option_bytes.boot_addr = optiondata;
+ } else {
+ /* for F42x/43x/469/479 it contains 12 additional protection bits */
+ stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
+ }
+ }
+
+ if (stm32x_info->has_optcr2_pcrop) {
+ retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+
+ stm32x_info->option_bytes.optcr2_pcrop = optiondata;
+ if (stm32x_info->has_optcr2_pcrop &&
+ (stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
+ LOG_INFO("PCROP Engaged");
+ }
+ } else {
+ stm32x_info->option_bytes.optcr2_pcrop = 0x0;
}
if (stm32x_info->option_bytes.RDP != 0xAA)
@@ -334,7 +394,7 @@ static int stm32x_write_options(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = NULL;
struct target *target = bank->target;
- uint32_t optiondata;
+ uint32_t optiondata, optiondata2;
stm32x_info = bank->driver_priv;
@@ -343,36 +403,56 @@ static int stm32x_write_options(struct flash_bank *bank)
return retval;
/* rebuild option data */
- optiondata = stm32x_info->option_bytes.user_options;
- buf_set_u32(&optiondata, 8, 8, stm32x_info->option_bytes.RDP);
- buf_set_u32(&optiondata, 16, 12, stm32x_info->option_bytes.protection);
-
- /* program options */
- retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
- if (retval != ERROR_OK)
- return retval;
+ optiondata = stm32x_info->option_bytes.user_options & 0xfc;
+ optiondata |= stm32x_info->option_bytes.RDP << 8;
+ optiondata |= (stm32x_info->option_bytes.protection &
+ (~(0xffff << stm32x_info->protection_bits))) << 16;
+
+ if (stm32x_info->has_extra_options) {
+ /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
+ optiondata |= (stm32x_info->option_bytes.user_options &
+ ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
+ }
- if (stm32x_info->has_large_mem) {
+ if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
+ if (stm32x_info->has_boot_addr) {
+ /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
+ optiondata2 = stm32x_info->option_bytes.boot_addr;
+ } else {
+ /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
+ optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
+ }
- uint32_t optiondata2 = 0;
- buf_set_u32(&optiondata2, 16, 12, stm32x_info->option_bytes.protection >> 12);
retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
if (retval != ERROR_OK)
return retval;
}
+ /* program extra pcrop register */
+ if (stm32x_info->has_optcr2_pcrop) {
+ retval = target_write_u32(target, STM32_FLASH_OPTCR2,
+ stm32x_info->option_bytes.optcr2_pcrop);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* program options */
+ retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+
/* start programming cycle */
- retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPT_START);
+ retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
if (retval != ERROR_OK)
return retval;
- /* wait for completion */
- retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
+ /* wait for completion, this might trigger a security erase and take a while */
+ retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
/* relock registers */
- retval = target_write_u32(target, STM32_FLASH_OPTCR, OPT_LOCK);
+ retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
if (retval != ERROR_OK)
return retval;
@@ -382,6 +462,8 @@ static int stm32x_write_options(struct flash_bank *bank)
static int stm32x_protect_check(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
+ struct flash_sector *prot_blocks;
+ int num_prot_blocks;
/* read write protection settings */
int retval = stm32x_read_options(bank);
@@ -390,13 +472,18 @@ static int stm32x_protect_check(struct flash_bank *bank)
return retval;
}
- for (int i = 0; i < bank->num_sectors; i++) {
- if (stm32x_info->option_bytes.protection & (1 << i))
- bank->sectors[i].is_protected = 0;
- else
- bank->sectors[i].is_protected = 1;
+ if (bank->prot_blocks) {
+ num_prot_blocks = bank->num_prot_blocks;
+ prot_blocks = bank->prot_blocks;
+ } else {
+ num_prot_blocks = bank->num_sectors;
+ prot_blocks = bank->sectors;
}
+ for (int i = 0; i < num_prot_blocks; i++)
+ prot_blocks[i].is_protected =
+ ~(stm32x_info->option_bytes.protection >> i) & 1;
+
return ERROR_OK;
}
@@ -405,8 +492,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
struct target *target = bank->target;
int i;
- assert(first < bank->num_sectors);
- assert(last < bank->num_sectors);
+ assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -467,7 +553,6 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
}
for (int i = first; i <= last; i++) {
-
if (set)
stm32x_info->option_bytes.protection &= ~(1 << i);
else
@@ -481,7 +566,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_OK;
}
-static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
@@ -504,10 +589,11 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
0x47, 0x45, /* cmp r7, r8 */
0xF7, 0xD0, /* beq wait_fifo */
- 0xDF, 0xF8, 0x30, 0x60, /* ldr r6, STM32_PROG16 */
+ 0xDF, 0xF8, 0x34, 0x60, /* ldr r6, STM32_PROG16 */
0x26, 0x61, /* str r6, [r4, #STM32_FLASH_CR_OFFSET] */
0x37, 0xF8, 0x02, 0x6B, /* ldrh r6, [r7], #0x02 */
0x22, 0xF8, 0x02, 0x6B, /* strh r6, [r2], #0x02 */
+ 0xBF, 0xF3, 0x4F, 0x8F, /* dsb sy */
/* busy: */
0xE6, 0x68, /* ldr r6, [r4, #STM32_FLASH_SR_OFFSET] */
0x16, 0xF4, 0x80, 0x3F, /* tst r6, #0x10000 */
@@ -521,7 +607,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
0x47, 0x60, /* str r7, [r0, #4] */
0x01, 0x3B, /* subs r3, r3, #1 */
0x13, 0xB1, /* cbz r3, exit */
- 0xE1, 0xE7, /* b wait_fifo */
+ 0xDF, 0xE7, /* b wait_fifo */
/* error: */
0x00, 0x21, /* movs r1, #0 */
0x41, 0x60, /* str r1, [r0, #4] */
@@ -537,11 +623,11 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
&write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
retval = target_write_buffer(target, write_algorithm->address,
sizeof(stm32x_flash_write_code),
- (uint8_t *)stm32x_flash_write_code);
+ stm32x_flash_write_code);
if (retval != ERROR_OK)
return retval;
@@ -556,7 +642,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- };
+ }
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
@@ -589,7 +675,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
LOG_ERROR("flash memory write protected");
if (error != 0) {
- LOG_ERROR("flash write failed = %08x", error);
+ LOG_ERROR("flash write failed = %08" PRIx32, error);
/* Clear but report errors */
target_write_u32(target, STM32_FLASH_SR, error);
retval = ERROR_FAIL;
@@ -608,7 +694,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
return retval;
}
-static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
@@ -707,14 +793,31 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
}
-static void setup_sector(struct flash_bank *bank, int start, int num, int size)
+static int setup_sector(struct flash_bank *bank, int start, int num, int size)
{
+
for (int i = start; i < (start + num) ; i++) {
assert(i < bank->num_sectors);
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
+ LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
}
+
+ return start + num;
+}
+
+static void setup_bank(struct flash_bank *bank, int start,
+ uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
+{
+ int remain;
+
+ start = setup_sector(bank, start, 4, (max_sector_size_in_kb / 8) * 1024);
+ start = setup_sector(bank, start, 1, (max_sector_size_in_kb / 2) * 1024);
+
+ /* remaining sectors all of size max_sector_size_in_kb */
+ remain = (flash_size_in_kb / max_sector_size_in_kb) - 1;
+ start = setup_sector(bank, start, remain, max_sector_size_in_kb * 1024);
}
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
@@ -752,40 +855,107 @@ static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- int i;
+ int i, num_prot_blocks;
uint16_t flash_size_in_kb;
+ uint32_t flash_size_reg = 0x1FFF7A22;
+ uint16_t max_sector_size_in_kb = 128;
uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t base_address = 0x08000000;
stm32x_info->probed = 0;
stm32x_info->has_large_mem = false;
+ stm32x_info->has_boot_addr = false;
+ stm32x_info->has_extra_options = false;
+ stm32x_info->has_optcr2_pcrop = false;
+ stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
+ num_prot_blocks = 0;
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->num_sectors = 0;
+ bank->sectors = NULL;
+ }
+
+ if (bank->prot_blocks) {
+ free(bank->prot_blocks);
+ bank->num_prot_blocks = 0;
+ bank->prot_blocks = NULL;
+ }
/* read stm32 device id register */
int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+ device_id &= 0xfff; /* only bits 0-11 are used further on */
- /* set max flash size depending on family */
- switch (device_id & 0xfff) {
- case 0x411:
- case 0x413:
+ /* set max flash size depending on family, id taken from AN2606 */
+ switch (device_id) {
+ case 0x411: /* F20x/21x */
+ case 0x413: /* F40x/41x */
max_flash_size_in_kb = 1024;
break;
- case 0x419:
+
+ case 0x419: /* F42x/43x */
+ case 0x434: /* F469/479 */
+ stm32x_info->has_extra_options = true;
max_flash_size_in_kb = 2048;
break;
- case 0x423:
+
+ case 0x423: /* F401xB/C */
max_flash_size_in_kb = 256;
break;
+
+ case 0x421: /* F446 */
+ case 0x431: /* F411 */
+ case 0x433: /* F401xD/E */
+ case 0x441: /* F412 */
+ max_flash_size_in_kb = 512;
+ break;
+
+ case 0x458: /* F410 */
+ max_flash_size_in_kb = 128;
+ break;
+
+ case 0x449: /* F74x/75x */
+ max_flash_size_in_kb = 1024;
+ max_sector_size_in_kb = 256;
+ flash_size_reg = 0x1FF0F442;
+ stm32x_info->has_extra_options = true;
+ stm32x_info->has_boot_addr = true;
+ break;
+
+ case 0x451: /* F76x/77x */
+ max_flash_size_in_kb = 2048;
+ max_sector_size_in_kb = 256;
+ flash_size_reg = 0x1FF0F442;
+ stm32x_info->has_extra_options = true;
+ stm32x_info->has_boot_addr = true;
+ break;
+
+ case 0x452: /* F72x/73x */
+ max_flash_size_in_kb = 512;
+ flash_size_reg = 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
+ stm32x_info->has_extra_options = true;
+ stm32x_info->has_boot_addr = true;
+ stm32x_info->has_optcr2_pcrop = true;
+ break;
+
+ case 0x463: /* F413x/423x */
+ max_flash_size_in_kb = 1536;
+ stm32x_info->has_extra_options = true;
+ stm32x_info->protection_bits = 15;
+ num_prot_blocks = 15;
+ break;
+
default:
LOG_WARNING("Cannot identify target as a STM32 family.");
return ERROR_FAIL;
}
/* get flash size from target. */
- retval = target_read_u16(target, 0x1FFF7A22, &flash_size_in_kb);
+ retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
@@ -802,59 +972,101 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
- /* only devices with > 1024kB have dual banks */
- if (flash_size_in_kb > 1024)
- stm32x_info->has_large_mem = true;
-
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
- /* calculate numbers of pages */
- int num_pages = (flash_size_in_kb / 128) + 4;
-
- /* check for larger 2048 bytes devices */
- if (stm32x_info->has_large_mem)
- num_pages += 4;
-
- /* check that calculation result makes sense */
- assert(num_pages > 0);
+ /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
+ if ((device_id == 0x419) || (device_id == 0x434)) {
+ uint32_t optiondata;
+ retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("unable to read option bytes");
+ return retval;
+ }
+ if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
+ stm32x_info->has_large_mem = true;
+ LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ } else {
+ stm32x_info->has_large_mem = false;
+ LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ }
+ }
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
+ /* F76x/77x devices have a dual bank option */
+ if (device_id == 0x451) {
+ uint32_t optiondata;
+ retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("unable to read option bytes");
+ return retval;
+ }
+ if (optiondata & OPTCR_NDBANK) {
+ stm32x_info->has_large_mem = false;
+ LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ } else {
+ stm32x_info->has_large_mem = true;
+ max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
+ LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ }
}
+ /* calculate numbers of pages */
+ int num_pages = flash_size_in_kb / max_sector_size_in_kb
+ + (stm32x_info->has_large_mem ? 8 : 4);
+
bank->base = base_address;
bank->num_sectors = num_pages;
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ for (i = 0; i < num_pages; i++) {
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 0;
+ }
bank->size = 0;
+ LOG_DEBUG("allocated %d sectors", num_pages);
- /* fixed memory */
- setup_sector(bank, 0, 4, 16 * 1024);
- setup_sector(bank, 4, 1, 64 * 1024);
-
- /* dynamic memory */
- setup_sector(bank, 4 + 1, MIN(12, num_pages) - 5, 128 * 1024);
-
- if (stm32x_info->has_large_mem) {
-
- /* fixed memory for larger devices */
- setup_sector(bank, 12, 4, 16 * 1024);
- setup_sector(bank, 16, 1, 64 * 1024);
+ /* F76x/77x in dual bank mode */
+ if ((device_id == 0x451) && stm32x_info->has_large_mem)
+ num_prot_blocks = num_pages >> 1;
- /* dynamic memory for larger devices */
- setup_sector(bank, 16 + 1, num_pages - 5 - 12, 128 * 1024);
+ if (num_prot_blocks) {
+ bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
+ for (i = 0; i < num_prot_blocks; i++)
+ bank->prot_blocks[i].is_protected = 0;
+ LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
}
- for (i = 0; i < num_pages; i++) {
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = 0;
+ if (stm32x_info->has_large_mem) {
+ /* dual-bank */
+ setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
+ setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
+ max_sector_size_in_kb);
+
+ /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
+ if (device_id == 0x451) {
+ for (i = 0; i < num_prot_blocks; i++) {
+ bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
+ bank->prot_blocks[i].size = bank->sectors[i << 1].size << 1;
+ }
+ }
+ } else {
+ /* single-bank */
+ setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
+
+ /* F413/F423, sectors 14 and 15 share one common protection bit */
+ if (device_id == 0x463) {
+ for (i = 0; i < num_prot_blocks; i++) {
+ bank->prot_blocks[i].offset = bank->sectors[i].offset;
+ bank->prot_blocks[i].size = bank->sectors[i].size;
+ }
+ bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
+ }
}
+ bank->num_prot_blocks = num_prot_blocks;
+ assert((bank->size >> 10) == flash_size_in_kb);
stm32x_info->probed = 1;
-
return ERROR_OK;
}
@@ -904,11 +1116,24 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
case 0x2003:
rev_str = "X";
break;
+
+ case 0x2007:
+ rev_str = "1";
+ break;
+
+ case 0x200F:
+ rev_str = "V";
+ break;
+
+ case 0x201F:
+ rev_str = "2";
+ break;
}
break;
case 0x413:
case 0x419:
+ case 0x434:
device_str = "STM32F4xx";
switch (rev_id) {
@@ -923,10 +1148,32 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
case 0x1003:
rev_str = "Y";
break;
+
+ case 0x1007:
+ rev_str = "1";
+ break;
+
+ case 0x2001:
+ rev_str = "3";
+ break;
+ }
+ break;
+
+ case 0x421:
+ device_str = "STM32F446";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
}
break;
case 0x423:
+ case 0x431:
+ case 0x433:
+ case 0x458:
+ case 0x441:
device_str = "STM32F4xx (Low Power)";
switch (rev_id) {
@@ -937,11 +1184,63 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
case 0x1001:
rev_str = "Z";
break;
+
+ case 0x2000:
+ rev_str = "B";
+ break;
+
+ case 0x3000:
+ rev_str = "C";
+ break;
+ }
+ break;
+
+ case 0x449:
+ device_str = "STM32F7[4|5]x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+ }
+ break;
+
+ case 0x451:
+ device_str = "STM32F7[6|7]x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ case 0x452:
+ device_str = "STM32F7[2|3]x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ case 0x463:
+ device_str = "STM32F4[1|2]3";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
}
break;
default:
- snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4\n");
+ snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
return ERROR_FAIL;
}
@@ -970,8 +1269,8 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
target = bank->target;
if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
+ LOG_INFO("Target not halted");
+ /* return ERROR_TARGET_NOT_HALTED; */
}
if (stm32x_read_options(bank) != ERROR_OK) {
@@ -1009,8 +1308,8 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
target = bank->target;
if (target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
+ LOG_INFO("Target not halted");
+ /* return ERROR_TARGET_NOT_HALTED; */
}
if (stm32x_read_options(bank) != ERROR_OK) {
@@ -1021,6 +1320,9 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
/* clear readout protection and complementary option bytes
* this will also force a device unlock if set */
stm32x_info->option_bytes.RDP = 0xAA;
+ if (stm32x_info->has_optcr2_pcrop) {
+ stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1 << bank->num_sectors);
+ }
if (stm32x_write_options(bank) != ERROR_OK) {
command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
@@ -1037,6 +1339,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
static int stm32x_mass_erase(struct flash_bank *bank)
{
int retval;
+ uint32_t flash_mer;
struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = NULL;
@@ -1053,17 +1356,19 @@ static int stm32x_mass_erase(struct flash_bank *bank)
/* mass erase flash memory */
if (stm32x_info->has_large_mem)
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_MER1);
+ flash_mer = FLASH_MER | FLASH_MER1;
else
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
+ flash_mer = FLASH_MER;
+
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
- FLASH_MER | FLASH_STRT);
+ flash_mer | FLASH_STRT);
if (retval != ERROR_OK)
return retval;
- retval = stm32x_wait_status_busy(bank, 30000);
+ retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
@@ -1102,6 +1407,155 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
return retval;
}
+COMMAND_HANDLER(stm32f2x_handle_options_read_command)
+{
+ int retval;
+ struct flash_bank *bank;
+ struct stm32x_flash_bank *stm32x_info = NULL;
+
+ if (CMD_ARGC != 1) {
+ command_print(CMD_CTX, "stm32f2x options_read ");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32x_read_options(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ stm32x_info = bank->driver_priv;
+ if (stm32x_info->has_extra_options) {
+ if (stm32x_info->has_boot_addr) {
+ uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
+
+ command_print(CMD_CTX, "stm32f2x user_options 0x%03X,"
+ " boot_add0 0x%04X, boot_add1 0x%04X",
+ stm32x_info->option_bytes.user_options,
+ boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
+ if (stm32x_info->has_optcr2_pcrop) {
+ command_print(CMD_CTX, "stm32f2x optcr2_pcrop 0x%08X",
+ stm32x_info->option_bytes.optcr2_pcrop);
+ }
+ } else {
+ command_print(CMD_CTX, "stm32f2x user_options 0x%03X",
+ stm32x_info->option_bytes.user_options);
+ }
+ } else {
+ command_print(CMD_CTX, "stm32f2x user_options 0x%02X",
+ stm32x_info->option_bytes.user_options);
+
+ }
+
+ return retval;
+}
+
+COMMAND_HANDLER(stm32f2x_handle_options_write_command)
+{
+ int retval;
+ struct flash_bank *bank;
+ struct stm32x_flash_bank *stm32x_info = NULL;
+ uint16_t user_options, boot_addr0, boot_addr1, options_mask;
+
+ if (CMD_ARGC < 1) {
+ command_print(CMD_CTX, "stm32f2x options_write ...");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = stm32x_read_options(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ stm32x_info = bank->driver_priv;
+ if (stm32x_info->has_boot_addr) {
+ if (CMD_ARGC != 4) {
+ command_print(CMD_CTX, "stm32f2x options_write "
+ " ");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
+ COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
+ stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
+ } else {
+ if (CMD_ARGC != 2) {
+ command_print(CMD_CTX, "stm32f2x options_write ");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ }
+
+ COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
+ options_mask = !stm32x_info->has_extra_options ? ~0xfc :
+ ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
+ if (user_options & options_mask) {
+ command_print(CMD_CTX, "stm32f2x invalid user_options");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ stm32x_info->option_bytes.user_options = user_options;
+
+ if (stm32x_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "stm32f2x failed to write options");
+ return ERROR_OK;
+ }
+
+ /* switching between single- and dual-bank modes requires re-probe */
+ /* ... and reprogramming of whole flash */
+ stm32x_info->probed = 0;
+
+ command_print(CMD_CTX, "stm32f2x write options complete.\n"
+ "INFO: a reset or power cycle is required "
+ "for the new settings to take effect.");
+ return retval;
+}
+
+COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
+{
+ int retval;
+ struct flash_bank *bank;
+ struct stm32x_flash_bank *stm32x_info = NULL;
+ uint32_t optcr2_pcrop;
+
+ if (CMD_ARGC != 2) {
+ command_print(CMD_CTX, "stm32f2x optcr2_write ");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ stm32x_info = bank->driver_priv;
+ if (!stm32x_info->has_optcr2_pcrop) {
+ command_print(CMD_CTX, "no optcr2 register");
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ command_print(CMD_CTX, "INFO: To disable PCROP, set PCROP_RDP"
+ " with PCROPi bits STILL SET, then\nlock device and"
+ " finally unlock it. Clears PCROP and mass erases flash.");
+
+ retval = stm32x_read_options(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
+ stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
+
+ if (stm32x_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "stm32f2x failed to write options");
+ return ERROR_OK;
+ }
+
+ command_print(CMD_CTX, "stm32f2x optcr2_write complete.");
+ return retval;
+}
+
static const struct command_registration stm32x_exec_command_handlers[] = {
{
.name = "lock",
@@ -1124,6 +1578,28 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.usage = "bank_id",
.help = "Erase entire flash device.",
},
+ {
+ .name = "options_read",
+ .handler = stm32f2x_handle_options_read_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Read and display device option bytes.",
+ },
+ {
+ .name = "options_write",
+ .handler = stm32f2x_handle_options_write_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id user_options [ boot_add0 boot_add1 ]",
+ .help = "Write option bytes",
+ },
+ {
+ .name = "optcr2_write",
+ .handler = stm32f2x_handle_optcr2_write_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id optcr2",
+ .help = "Write optcr2 word",
+ },
+
COMMAND_REGISTRATION_DONE
};