X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f1x.c;h=ae2991553ac465ee66a66a050a671da8318ea2b2;hp=02ab8c990d55b4c79b37dfa4731a2a2d73fba11e;hb=346ce2f13f48f36550b2a1a3862801496e20c81b;hpb=81b4ef6ee52fd0e897f4c2ecc6a173161abb930f
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 02ab8c990d..ae2991553a 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -19,10 +19,9 @@
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see . *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -71,14 +70,15 @@
/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER (1 << 2)
-#define FLASH_OPTPG (1 << 4)
-#define FLASH_OPTER (1 << 5)
-#define FLASH_STRT (1 << 6)
-#define FLASH_LOCK (1 << 7)
-#define FLASH_OPTWRE (1 << 9)
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER (1 << 2)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_STRT (1 << 6)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_OPTWRE (1 << 9)
+#define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
/* FLASH_SR register bits */
@@ -101,26 +101,37 @@
#define KEY1 0x45670123
#define KEY2 0xCDEF89AB
-struct stm32x_options
-{
- uint16_t RDP;
- uint16_t user_options;
- uint16_t protection[4];
+/* timeout values */
+
+#define FLASH_WRITE_TIMEOUT 10
+#define FLASH_ERASE_TIMEOUT 100
+
+struct stm32x_options {
+ uint8_t rdp;
+ uint8_t user;
+ uint16_t data;
+ uint32_t protection;
};
-struct stm32x_flash_bank
-{
+struct stm32x_flash_bank {
struct stm32x_options option_bytes;
- struct working_area *write_algorithm;
int ppage_size;
int probed;
bool has_dual_banks;
/* used to access dual flash bank stm32xl */
+ bool can_load_options;
uint32_t register_base;
+ uint8_t default_rdp;
+ int user_data_offset;
+ int option_offset;
+ uint32_t user_bank_size;
};
static int stm32x_mass_erase(struct flash_bank *bank);
+static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t address, uint32_t count);
/* flash bank stm32x 0 0
*/
@@ -129,17 +140,16 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
struct stm32x_flash_bank *stm32x_info;
if (CMD_ARGC < 6)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
- bank->driver_priv = stm32x_info;
- stm32x_info->write_algorithm = NULL;
+ bank->driver_priv = stm32x_info;
stm32x_info->probed = 0;
stm32x_info->has_dual_banks = false;
+ stm32x_info->can_load_options = false;
stm32x_info->register_base = FLASH_REG_BASE_B0;
+ stm32x_info->user_bank_size = bank->size;
return ERROR_OK;
}
@@ -163,37 +173,32 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
int retval = ERROR_OK;
/* wait for busy to clear */
- for (;;)
- {
+ for (;;) {
retval = stm32x_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
if ((status & FLASH_BSY) == 0)
break;
- if (timeout-- <= 0)
- {
+ if (timeout-- <= 0) {
LOG_ERROR("timed out waiting for flash");
return ERROR_FAIL;
}
alive_sleep(1);
}
- if (status & FLASH_WRPRTERR)
- {
+ if (status & FLASH_WRPRTERR) {
LOG_ERROR("stm32x device protected");
retval = ERROR_FAIL;
}
- if (status & FLASH_PGERR)
- {
+ if (status & FLASH_PGERR) {
LOG_ERROR("stm32x device programming failed");
retval = ERROR_FAIL;
}
/* Clear but report errors */
- if (status & (FLASH_WRPRTERR | FLASH_PGERR))
- {
+ if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
/* If this operation fails, we ignore it and report the original
* retval
*/
@@ -203,14 +208,13 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
return retval;
}
-int stm32x_check_operation_supported(struct flash_bank *bank)
+static int stm32x_check_operation_supported(struct flash_bank *bank)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
/* if we have a dual flash bank device then
* we need to perform option byte stuff on bank0 only */
- if (stm32x_info->register_base != FLASH_REG_BASE_B0)
- {
+ if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
LOG_ERROR("Option Byte Operation's must use bank0");
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -220,43 +224,47 @@ int stm32x_check_operation_supported(struct flash_bank *bank)
static int stm32x_read_options(struct flash_bank *bank)
{
- uint32_t optiondata;
- struct stm32x_flash_bank *stm32x_info = NULL;
+ struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
+ uint32_t option_bytes;
+ int retval;
- stm32x_info = bank->driver_priv;
+ /* read user and read protection option bytes */
+ retval = target_read_u32(target, STM32_OB_RDP, &option_bytes);
+ if (retval != ERROR_OK)
+ return retval;
- /* read current option bytes */
- int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
+ stm32x_info->option_bytes.rdp = option_bytes & 0xFF;
+ stm32x_info->option_bytes.user = (option_bytes >> 16) & 0xFF;
+
+ /* read user data option bytes */
+ retval = target_read_u32(target, STM32_OB_DATA0, &option_bytes);
if (retval != ERROR_OK)
return retval;
- stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
- stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
+ stm32x_info->option_bytes.data = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
- if (optiondata & (1 << OPT_READOUT))
- LOG_INFO("Device Security Bit Set");
+ /* read write protection option bytes */
+ retval = target_read_u32(target, STM32_OB_WRP0, &option_bytes);
+ if (retval != ERROR_OK)
+ return retval;
+
+ stm32x_info->option_bytes.protection = ((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF);
- /* each bit refers to a 4bank protection */
- retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
+ retval = target_read_u32(target, STM32_OB_WRP2, &option_bytes);
if (retval != ERROR_OK)
return retval;
- stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
- stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
- stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
- stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
+ stm32x_info->option_bytes.protection |= (((option_bytes >> 8) & 0xFF00) | (option_bytes & 0xFF)) << 16;
return ERROR_OK;
}
static int stm32x_erase_options(struct flash_bank *bank)
{
- struct stm32x_flash_bank *stm32x_info = NULL;
+ struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
- stm32x_info = bank->driver_priv;
-
/* read current options */
stm32x_read_options(bank);
@@ -285,13 +293,13 @@ static int stm32x_erase_options(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- retval = stm32x_wait_status_busy(bank, 10);
+ retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
- /* clear readout protection and complementary option bytes
+ /* clear read protection option byte
* this will also force a device unlock if set */
- stm32x_info->option_bytes.RDP = 0x5AA5;
+ stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
return ERROR_OK;
}
@@ -324,59 +332,23 @@ static int stm32x_write_options(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- /* write user option byte */
- retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
- return retval;
-
- /* write protection byte 1 */
- retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
- return retval;
-
- /* write protection byte 2 */
- retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
- return retval;
-
- /* write protection byte 3 */
- retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
- return retval;
-
- /* write protection byte 4 */
- retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
- return retval;
-
- /* write readout protection bit */
- retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
- if (retval != ERROR_OK)
- return retval;
-
- retval = stm32x_wait_status_busy(bank, 10);
- if (retval != ERROR_OK)
+ uint8_t opt_bytes[16];
+
+ target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
+ target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
+ target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
+ target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
+ target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
+ target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
+ target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
+ target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
+
+ retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
+ if (retval != ERROR_OK) {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
+ LOG_ERROR("working area required to erase options bytes");
return retval;
+ }
retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
if (retval != ERROR_OK)
@@ -388,77 +360,21 @@ static int stm32x_write_options(struct flash_bank *bank)
static int stm32x_protect_check(struct flash_bank *bank)
{
struct target *target = bank->target;
- struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
-
uint32_t protection;
- int i, s;
- int num_bits;
- int set;
-
- if (target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
int retval = stm32x_check_operation_supported(bank);
if (ERROR_OK != retval)
return retval;
- /* medium density - each bit refers to a 4bank protection
- * high density - each bit refers to a 2bank protection */
+ /* medium density - each bit refers to a 4 sector protection block
+ * high density - each bit refers to a 2 sector protection block
+ * bit 31 refers to all remaining sectors in a bank */
retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
if (retval != ERROR_OK)
return retval;
- /* medium density - each protection bit is for 4 * 1K pages
- * high density - each protection bit is for 2 * 2K pages */
- num_bits = (bank->num_sectors / stm32x_info->ppage_size);
-
- if (stm32x_info->ppage_size == 2)
- {
- /* high density flash/connectivity line protection */
-
- set = 1;
-
- if (protection & (1 << 31))
- set = 0;
-
- /* bit 31 controls sector 62 - 255 protection for high density
- * bit 31 controls sector 62 - 127 protection for connectivity line */
- for (s = 62; s < bank->num_sectors; s++)
- {
- bank->sectors[s].is_protected = set;
- }
-
- if (bank->num_sectors > 61)
- num_bits = 31;
-
- for (i = 0; i < num_bits; i++)
- {
- set = 1;
-
- if (protection & (1 << i))
- set = 0;
-
- for (s = 0; s < stm32x_info->ppage_size; s++)
- bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
- }
- }
- else
- {
- /* low/medium density flash protection */
- for (i = 0; i < num_bits; i++)
- {
- set = 1;
-
- if (protection & (1 << i))
- set = 0;
-
- for (s = 0; s < stm32x_info->ppage_size; s++)
- bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
- }
- }
+ for (int i = 0; i < bank->num_prot_blocks; i++)
+ bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
return ERROR_OK;
}
@@ -468,16 +384,13 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
struct target *target = bank->target;
int i;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first == 0) && (last == (bank->num_sectors - 1)))
- {
return stm32x_mass_erase(bank);
- }
/* unlock flash registers */
int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
@@ -487,8 +400,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
- for (i = first; i <= last; i++)
- {
+ for (i = first; i <= last; i++) {
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
if (retval != ERROR_OK)
return retval;
@@ -501,7 +413,7 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
- retval = stm32x_wait_status_busy(bank, 100);
+ retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
@@ -517,208 +429,77 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
{
- struct stm32x_flash_bank *stm32x_info = NULL;
struct target *target = bank->target;
- uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
- int i, reg, bit;
- int status;
- uint32_t protection;
-
- stm32x_info = bank->driver_priv;
+ struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
int retval = stm32x_check_operation_supported(bank);
- if (ERROR_OK != retval)
- return retval;
-
- if ((first % stm32x_info->ppage_size) != 0)
- {
- LOG_WARNING("aligned start protect sector to a %d sector boundary",
- stm32x_info->ppage_size);
- first = first - (first % stm32x_info->ppage_size);
- }
- if (((last + 1) % stm32x_info->ppage_size) != 0)
- {
- LOG_WARNING("aligned end protect sector to a %d sector boundary",
- stm32x_info->ppage_size);
- last++;
- last = last - (last % stm32x_info->ppage_size);
- last--;
- }
-
- /* medium density - each bit refers to a 4bank protection
- * high density - each bit refers to a 2bank protection */
- retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
if (retval != ERROR_OK)
return retval;
- prot_reg[0] = (uint16_t)protection;
- prot_reg[1] = (uint16_t)(protection >> 8);
- prot_reg[2] = (uint16_t)(protection >> 16);
- prot_reg[3] = (uint16_t)(protection >> 24);
-
- if (stm32x_info->ppage_size == 2)
- {
- /* high density flash */
-
- /* bit 7 controls sector 62 - 255 protection */
- if (last > 61)
- {
- if (set)
- prot_reg[3] &= ~(1 << 7);
- else
- prot_reg[3] |= (1 << 7);
- }
-
- if (first > 61)
- first = 62;
- if (last > 61)
- last = 61;
-
- for (i = first; i <= last; i++)
- {
- reg = (i / stm32x_info->ppage_size) / 8;
- bit = (i / stm32x_info->ppage_size) - (reg * 8);
-
- if (set)
- prot_reg[reg] &= ~(1 << bit);
- else
- prot_reg[reg] |= (1 << bit);
- }
- }
- else
- {
- /* medium density flash */
- for (i = first; i <= last; i++)
- {
- reg = (i / stm32x_info->ppage_size) / 8;
- bit = (i / stm32x_info->ppage_size) - (reg * 8);
-
- if (set)
- prot_reg[reg] &= ~(1 << bit);
- else
- prot_reg[reg] |= (1 << bit);
- }
+ retval = stm32x_erase_options(bank);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("stm32x failed to erase options");
+ return retval;
}
- if ((status = stm32x_erase_options(bank)) != ERROR_OK)
- return status;
-
- stm32x_info->option_bytes.protection[0] = prot_reg[0];
- stm32x_info->option_bytes.protection[1] = prot_reg[1];
- stm32x_info->option_bytes.protection[2] = prot_reg[2];
- stm32x_info->option_bytes.protection[3] = prot_reg[3];
+ for (int i = first; i <= last; i++) {
+ if (set)
+ stm32x_info->option_bytes.protection &= ~(1 << i);
+ else
+ stm32x_info->option_bytes.protection |= (1 << i);
+ }
return stm32x_write_options(bank);
}
-static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
- uint32_t offset, uint32_t count)
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t address, uint32_t count)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
struct working_area *source;
- uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
- /* see contrib/loaders/flash/stm32f1x.S for src */
-
static const uint8_t stm32x_flash_write_code[] = {
- /* #define STM32_FLASH_CR_OFFSET 0x10 */
- /* #define STM32_FLASH_SR_OFFSET 0x0C */
- /* wait_fifo: */
- 0x16, 0x68, /* ldr r6, [r2, #0] */
- 0x00, 0x2e, /* cmp r6, #0 */
- 0x1a, 0xd0, /* beq exit */
- 0x55, 0x68, /* ldr r5, [r2, #4] */
- 0xb5, 0x42, /* cmp r5, r6 */
- 0xf9, 0xd0, /* beq wait_fifo */
- 0x01, 0x26, /* movs r6, #1 */
- 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
- 0x2e, 0x88, /* ldrh r6, [r5, #0] */
- 0x26, 0x80, /* strh r6, [r4, #0] */
- 0x02, 0x35, /* adds r5, #2 */
- 0x02, 0x34, /* adds r4, #2 */
- /* busy: */
- 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
- 0x01, 0x27, /* movs r7, #1 */
- 0x3e, 0x42, /* tst r6, r7 */
- 0xfb, 0xd1, /* bne busy */
- 0x14, 0x27, /* movs r7, #0x14 */
- 0x3e, 0x42, /* tst r6, r7 */
- 0x08, 0xd1, /* bne error */
- 0x9d, 0x42, /* cmp r5, r3 */
- 0x01, 0xd3, /* bcc no_wrap */
- 0x15, 0x46, /* mov r5, r2 */
- 0x08, 0x35, /* adds r5, #8 */
- /* no_wrap: */
- 0x55, 0x60, /* str r5, [r2, #4] */
- 0x01, 0x39, /* subs r1, r1, #1 */
- 0x00, 0x29, /* cmp r1, #0 */
- 0x02, 0xd0, /* beq exit */
- 0xe3, 0xe7, /* b wait_fifo */
- /* error: */
- 0x00, 0x20, /* movs r0, #0 */
- 0x50, 0x60, /* str r0, [r2, #4] */
- /* exit: */
- 0x30, 0x46, /* mov r0, r6 */
- 0x00, 0xbe, /* bkpt #0 */
+#include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
- &stm32x_info->write_algorithm) != ERROR_OK)
- {
+ &write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- };
+ }
- if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
- sizeof(stm32x_flash_write_code),
- (uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
return retval;
+ }
/* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
- {
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
- buffer_size &= ~3UL; // Make sure it's 4 byte aligned
- if (buffer_size <= 256)
- {
- /* if we already allocated the writing code, but failed to get a
+ buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (stm32x_info->write_algorithm)
- target_free_working_area(target, stm32x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- };
-
- /* Set up working area. First word is write pointer, second word is read pointer,
- * rest is fifo data area. */
- uint32_t wp_addr = source->address;
- uint32_t rp_addr = source->address + 4;
- uint32_t fifo_start_addr = source->address + 8;
- uint32_t fifo_end_addr = source->address + source->size;
-
- uint32_t wp = fifo_start_addr;
- uint32_t rp = fifo_start_addr;
-
- retval = target_write_u32(target, wp_addr, wp);
- if (retval != ERROR_OK)
- return retval;
- retval = target_write_u32(target, rp_addr, rp);
- if (retval != ERROR_OK)
- return retval;
+ }
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
@@ -733,124 +514,34 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
buf_set_u32(reg_params[4].value, 0, 32, address);
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
- armv7m_info.core_mode = ARMV7M_MODE_ANY;
-
- /* Start up algorithm on target and let it idle while writing the first chunk */
- if ((retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
- stm32x_info->write_algorithm->address,
- 0,
- &armv7m_info)) != ERROR_OK)
- {
- LOG_ERROR("error starting stm32x flash write algorithm");
- goto cleanup;
- }
-
- while (count > 0)
- {
- retval = target_read_u32(target, rp_addr, &rp);
- if (retval != ERROR_OK)
- {
- LOG_ERROR("failed to get read pointer");
- break;
- }
+ armv7m_info.core_mode = ARM_MODE_THREAD;
- LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
+ retval = target_run_flash_async_algorithm(target, buffer, count, 2,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
- if (rp == 0)
- {
- LOG_ERROR("flash write algorithm aborted by target");
- retval = ERROR_FLASH_OPERATION_FAILED;
- break;
- }
-
- if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr)
- {
- LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
- break;
- }
-
- /* Count the number of bytes available in the fifo without
- * crossing the wrap around. Make sure to not fill it completely,
- * because that would make wp == rp and that's the empty condition. */
- uint32_t thisrun_bytes;
- if (rp > wp)
- thisrun_bytes = rp - wp - 2;
- else if (rp > fifo_start_addr)
- thisrun_bytes = fifo_end_addr - wp;
- else
- thisrun_bytes = fifo_end_addr - wp - 2;
-
- if (thisrun_bytes == 0)
- {
- /* Throttle polling a bit if transfer is (much) faster than flash
- * programming. The exact delay shouldn't matter as long as it's
- * less than buffer size / flash speed. This is very unlikely to
- * run when using high latency connections such as USB. */
- alive_sleep(10);
- continue;
- }
-
- /* Limit to the amount of data we actually want to write */
- if (thisrun_bytes > count * 2)
- thisrun_bytes = count * 2;
-
- /* Write data to fifo */
- retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
- if (retval != ERROR_OK)
- break;
-
- /* Update counters and wrap write pointer */
- buffer += thisrun_bytes;
- count -= thisrun_bytes / 2;
- wp += thisrun_bytes;
- if (wp >= fifo_end_addr)
- wp = fifo_start_addr;
-
- /* Store updated write pointer to target */
- retval = target_write_u32(target, wp_addr, wp);
- if (retval != ERROR_OK)
- break;
- }
-
- if (retval != ERROR_OK)
- {
- /* abort flash write algorithm on target */
- target_write_u32(target, wp_addr, 0);
- }
-
- int retval2;
- if ((retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
- 0,
- 10000,
- &armv7m_info)) != ERROR_OK)
- {
- LOG_ERROR("error waiting for stm32x flash write algorithm");
- retval = retval2;
- }
-
- if (retval == ERROR_FLASH_OPERATION_FAILED)
- {
+ if (retval == ERROR_FLASH_OPERATION_FAILED) {
LOG_ERROR("flash write failed at address 0x%"PRIx32,
buf_get_u32(reg_params[4].value, 0, 32));
- if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR)
- {
+ if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
LOG_ERROR("flash memory not erased before writing");
/* Clear but report errors */
- target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
+ target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
}
- if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR)
- {
+ if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
LOG_ERROR("flash memory write protected");
/* Clear but report errors */
- target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
+ target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
}
}
-cleanup:
target_free_working_area(target, source);
- target_free_working_area(target, stm32x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
@@ -861,240 +552,310 @@ cleanup:
return retval;
}
-static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
- uint32_t words_remaining = (count / 2);
- uint32_t bytes_remaining = (count & 0x00000001);
- uint32_t address = bank->base + offset;
- uint32_t bytes_written = 0;
- int retval;
+ uint8_t *new_buffer = NULL;
- if (bank->target->state != TARGET_HALTED)
- {
+ if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if (offset & 0x1)
- {
- LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
+ if (offset & 0x1) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
+ /* If there's an odd number of bytes, the data has to be padded. Duplicate
+ * the buffer and use the normal code path with a single block write since
+ * it's probably cheaper than to special case the last odd write using
+ * discrete accesses. */
+ if (count & 1) {
+ new_buffer = malloc(count + 1);
+ if (new_buffer == NULL) {
+ LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("odd number of bytes to write, padding with 0xff");
+ buffer = memcpy(new_buffer, buffer, count);
+ new_buffer[count++] = 0xff;
+ }
+
+ uint32_t words_remaining = count / 2;
+ int retval, retval2;
+
/* unlock flash registers */
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
- /* multiple half words (2-byte) to be programmed? */
- if (words_remaining > 0)
- {
- /* try using a block write */
- if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
- {
- if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
- {
- /* if block write failed (no sufficient working area),
- * we use normal (slow) single dword accesses */
- LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
- }
- }
- else
- {
- buffer += words_remaining * 2;
- address += words_remaining * 2;
- words_remaining = 0;
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
+ if (retval != ERROR_OK)
+ goto cleanup;
+
+ /* try using a block write */
+ retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
+
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single halfword accesses */
+ LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+
+ while (words_remaining > 0) {
+ uint16_t value;
+ memcpy(&value, buffer, sizeof(uint16_t));
+
+ retval = target_write_u16(target, bank->base + offset, value);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ retval = stm32x_wait_status_busy(bank, 5);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ words_remaining--;
+ buffer += 2;
+ offset += 2;
}
}
- if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
- return retval;
+reset_pg_and_lock:
+ retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
+ if (retval == ERROR_OK)
+ retval = retval2;
- while (words_remaining > 0)
- {
- uint16_t value;
- memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
+cleanup:
+ if (new_buffer)
+ free(new_buffer);
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
- if (retval != ERROR_OK)
- return retval;
- retval = target_write_u16(target, address, value);
- if (retval != ERROR_OK)
- return retval;
+ return retval;
+}
- retval = stm32x_wait_status_busy(bank, 5);
- if (retval != ERROR_OK)
- return retval;
+static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
+{
+ /* This check the device CPUID core register to detect
+ * the M0 from the M3 devices. */
+
+ struct target *target = bank->target;
+ uint32_t cpuid, device_id_register = 0;
+
+ /* Get the CPUID from the ARM Core
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
+ int retval = target_read_u32(target, 0xE000ED00, &cpuid);
+ if (retval != ERROR_OK)
+ return retval;
- bytes_written += 2;
- words_remaining--;
- address += 2;
+ if (((cpuid >> 4) & 0xFFF) == 0xC20) {
+ /* 0xC20 is M0 devices */
+ device_id_register = 0x40015800;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
+ /* 0xC23 is M3 devices */
+ device_id_register = 0xE0042000;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
+ /* 0xC24 is M4 devices */
+ device_id_register = 0xE0042000;
+ } else {
+ LOG_ERROR("Cannot identify target as a stm32x");
+ return ERROR_FAIL;
}
- if (bytes_remaining)
- {
- uint16_t value = 0xffff;
- memcpy(&value, buffer + bytes_written, bytes_remaining);
+ /* read stm32 device id register */
+ retval = target_read_u32(target, device_id_register, device_id);
+ if (retval != ERROR_OK)
+ return retval;
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
- if (retval != ERROR_OK)
- return retval;
- retval = target_write_u16(target, address, value);
- if (retval != ERROR_OK)
- return retval;
+ return retval;
+}
- retval = stm32x_wait_status_busy(bank, 5);
- if (retval != ERROR_OK)
- return retval;
+static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
+{
+ struct target *target = bank->target;
+ uint32_t cpuid, flash_size_reg;
+
+ int retval = target_read_u32(target, 0xE000ED00, &cpuid);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (((cpuid >> 4) & 0xFFF) == 0xC20) {
+ /* 0xC20 is M0 devices */
+ flash_size_reg = 0x1FFFF7CC;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
+ /* 0xC23 is M3 devices */
+ flash_size_reg = 0x1FFFF7E0;
+ } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
+ /* 0xC24 is M4 devices */
+ flash_size_reg = 0x1FFFF7CC;
+ } else {
+ LOG_ERROR("Cannot identify target as a stm32x");
+ return ERROR_FAIL;
}
- return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
+ retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval;
}
static int stm32x_probe(struct flash_bank *bank)
{
- struct target *target = bank->target;
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
- int i;
uint16_t flash_size_in_kb;
+ uint16_t max_flash_size_in_kb;
uint32_t device_id;
int page_size;
uint32_t base_address = 0x08000000;
stm32x_info->probed = 0;
stm32x_info->register_base = FLASH_REG_BASE_B0;
+ stm32x_info->user_data_offset = 10;
+ stm32x_info->option_offset = 0;
+
+ /* default factory read protection level 0 */
+ stm32x_info->default_rdp = 0xA5;
/* read stm32 device id register */
- int retval = target_read_u32(target, 0xE0042000, &device_id);
+ int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
- LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
- /* get flash size from target. */
- retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
- if (retval != ERROR_OK)
- {
- LOG_WARNING("failed reading flash size, default to max target family");
- /* failed reading flash size, default to max target family */
- flash_size_in_kb = 0xffff;
- }
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
- if ((device_id & 0xfff) == 0x410) {
- /* medium density - we have 1k pages
- * 4 pages for a protection area */
+ /* set page size, protection granularity and max flash size depending on family */
+ switch (device_id & 0xfff) {
+ case 0x410: /* medium density */
page_size = 1024;
stm32x_info->ppage_size = 4;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors incorrect on revA */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
- flash_size_in_kb = 128;
- }
- } else if ((device_id & 0xfff) == 0x412) {
- /* low density - we have 1k pages
- * 4 pages for a protection area */
+ max_flash_size_in_kb = 128;
+ break;
+ case 0x412: /* low density */
page_size = 1024;
stm32x_info->ppage_size = 4;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors incorrect on revA */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
- flash_size_in_kb = 32;
- }
- } else if ((device_id & 0xfff) == 0x414) {
- /* high density - we have 2k pages
- * 2 pages for a protection area */
+ max_flash_size_in_kb = 32;
+ break;
+ case 0x414: /* high density */
page_size = 2048;
stm32x_info->ppage_size = 2;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors incorrect on revZ */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
- flash_size_in_kb = 512;
- }
- } else if ((device_id & 0xfff) == 0x418) {
- /* connectivity line density - we have 2k pages
- * 2 pages for a protection area */
+ max_flash_size_in_kb = 512;
+ break;
+ case 0x418: /* connectivity line density */
page_size = 2048;
stm32x_info->ppage_size = 2;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors incorrect on revZ */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
- flash_size_in_kb = 256;
- }
- } else if ((device_id & 0xfff) == 0x420) {
- /* value line density - we have 1k pages
- * 4 pages for a protection area */
+ max_flash_size_in_kb = 256;
+ break;
+ case 0x420: /* value line density */
page_size = 1024;
stm32x_info->ppage_size = 4;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors may be incorrrect on early silicon */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
- flash_size_in_kb = 128;
- }
- } else if ((device_id & 0xfff) == 0x428) {
- /* value line High density - we have 2k pages
- * 4 pages for a protection area */
+ max_flash_size_in_kb = 128;
+ break;
+ case 0x422: /* stm32f302/3xb/c */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 256;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x446: /* stm32f303xD/E */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 512;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x428: /* value line High density */
page_size = 2048;
stm32x_info->ppage_size = 4;
-
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors may be incorrrect on early silicon */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
- flash_size_in_kb = 128;
- }
- } else if ((device_id & 0xfff) == 0x430) {
- /* xl line density - we have 2k pages
- * 2 pages for a protection area */
+ max_flash_size_in_kb = 128;
+ break;
+ case 0x430: /* xl line density (dual flash banks) */
page_size = 2048;
stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 1024;
stm32x_info->has_dual_banks = true;
+ break;
+ case 0x432: /* stm32f37x */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 256;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x438: /* stm32f33x */
+ case 0x439: /* stm32f302x6/8 */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 64;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x440: /* stm32f05x */
+ case 0x444: /* stm32f03x */
+ case 0x445: /* stm32f04x */
+ page_size = 1024;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 64;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x448: /* stm32f07x */
+ case 0x442: /* stm32f09x */
+ page_size = 2048;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 256;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ default:
+ LOG_WARNING("Cannot identify target as a STM32 family.");
+ return ERROR_FAIL;
+ }
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff)
- {
- /* number of sectors may be incorrrect on early silicon */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
- flash_size_in_kb = 1024;
- }
+ /* get flash size from target. */
+ retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
+
+ /* failed reading flash size or flash size invalid (early silicon),
+ * default to max target family */
+ if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
+ max_flash_size_in_kb);
+ flash_size_in_kb = max_flash_size_in_kb;
+ }
+ if (stm32x_info->has_dual_banks) {
/* split reported size into matching bank */
- if (bank->base != 0x08080000)
- {
+ if (bank->base != 0x08080000) {
/* bank 0 will be fixed 512k */
flash_size_in_kb = 512;
- }
- else
- {
+ } else {
flash_size_in_kb -= 512;
/* bank1 also uses a register offset */
stm32x_info->register_base = FLASH_REG_BASE_B1;
base_address = 0x08080000;
}
}
- else
- {
- LOG_WARNING("Cannot identify target as a STM32 family.");
- return ERROR_FAIL;
+
+ /* if the user sets the size manually then ignore the probed value
+ * this allows us to work around devices that have a invalid flash size register value */
+ if (stm32x_info->user_bank_size) {
+ LOG_INFO("ignoring flash probed value, using configured bank size");
+ flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
@@ -1108,24 +869,36 @@ static int stm32x_probe(struct flash_bank *bank)
/* check that calculation result makes sense */
assert(num_pages > 0);
- if (bank->sectors)
- {
+ if (bank->sectors) {
free(bank->sectors);
bank->sectors = NULL;
}
+ if (bank->prot_blocks) {
+ free(bank->prot_blocks);
+ bank->prot_blocks = NULL;
+ }
+
bank->base = base_address;
bank->size = (num_pages * page_size);
+
bank->num_sectors = num_pages;
- bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ bank->sectors = alloc_block_array(0, page_size, num_pages);
+ if (!bank->sectors)
+ return ERROR_FAIL;
- for (i = 0; i < num_pages; i++)
- {
- bank->sectors[i].offset = i * page_size;
- bank->sectors[i].size = page_size;
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = 1;
- }
+ /* calculate number of write protection blocks */
+ int num_prot_blocks = num_pages / stm32x_info->ppage_size;
+ if (num_prot_blocks > 32)
+ num_prot_blocks = 32;
+
+ bank->num_prot_blocks = num_prot_blocks;
+ bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
+ if (!bank->prot_blocks)
+ return ERROR_FAIL;
+
+ if (num_prot_blocks == 32)
+ bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
stm32x_info->probed = 1;
@@ -1147,157 +920,242 @@ COMMAND_HANDLER(stm32x_handle_part_id_command)
}
#endif
+static const char *get_stm32f0_revision(uint16_t rev_id)
+{
+ const char *rev_str = NULL;
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "1.0";
+ break;
+ case 0x2000:
+ rev_str = "2.0";
+ break;
+ }
+ return rev_str;
+}
+
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
{
- struct target *target = bank->target;
- uint32_t device_id;
- int printed;
+ uint32_t dbgmcu_idcode;
- /* read stm32 device id register */
- int retval = target_read_u32(target, 0xE0042000, &device_id);
+ /* read stm32 device id register */
+ int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
if (retval != ERROR_OK)
return retval;
- if ((device_id & 0xfff) == 0x410) {
- printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
- buf += printed;
- buf_size -= printed;
+ uint16_t device_id = dbgmcu_idcode & 0xfff;
+ uint16_t rev_id = dbgmcu_idcode >> 16;
+ const char *device_str;
+ const char *rev_str = NULL;
- switch (device_id >> 16)
- {
- case 0x0000:
- snprintf(buf, buf_size, "A");
- break;
+ switch (device_id) {
+ case 0x410:
+ device_str = "STM32F10x (Medium Density)";
- case 0x2000:
- snprintf(buf, buf_size, "B");
- break;
+ switch (rev_id) {
+ case 0x0000:
+ rev_str = "A";
+ break;
- case 0x2001:
- snprintf(buf, buf_size, "Z");
- break;
+ case 0x2000:
+ rev_str = "B";
+ break;
- case 0x2003:
- snprintf(buf, buf_size, "Y");
- break;
+ case 0x2001:
+ rev_str = "Z";
+ break;
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ case 0x2003:
+ rev_str = "Y";
+ break;
}
- } else if ((device_id & 0xfff) == 0x412) {
- printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x412:
+ device_str = "STM32F10x (Low Density)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
}
- } else if ((device_id & 0xfff) == 0x414) {
- printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x414:
+ device_str = "STM32F10x (High Density)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+
+ case 0x1003:
+ rev_str = "Y";
+ break;
}
- } else if ((device_id & 0xfff) == 0x418) {
- printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x418:
+ device_str = "STM32F10x (Connectivity)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
}
- } else if ((device_id & 0xfff) == 0x420) {
- printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x420:
+ device_str = "STM32F100 (Low/Medium Density)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
}
- } else if ((device_id & 0xfff) == 0x428) {
- printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- case 0x1001:
- snprintf(buf, buf_size, "Z");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x422:
+ device_str = "STM32F302xB/C";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+
+ case 0x1003:
+ rev_str = "Y";
+ break;
+
+ case 0x2000:
+ rev_str = "B";
+ break;
}
- } else if ((device_id & 0xfff) == 0x430) {
- printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
- buf += printed;
- buf_size -= printed;
-
- switch (device_id >> 16)
- {
- case 0x1000:
- snprintf(buf, buf_size, "A");
- break;
-
- default:
- snprintf(buf, buf_size, "unknown");
- break;
+ break;
+
+ case 0x428:
+ device_str = "STM32F100 (High Density)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
}
- }
- else
- {
- snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
+ break;
+
+ case 0x430:
+ device_str = "STM32F10x (XL Density)";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ case 0x432:
+ device_str = "STM32F37x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x2000:
+ rev_str = "B";
+ break;
+ }
+ break;
+
+ case 0x438:
+ device_str = "STM32F33x";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ case 0x439:
+ device_str = "STM32F302x6/8";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
+ break;
+ }
+ break;
+
+ case 0x444:
+ device_str = "STM32F03x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x440:
+ device_str = "STM32F05x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x445:
+ device_str = "STM32F04x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x446:
+ device_str = "STM32F303xD/E";
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+ }
+ break;
+
+ case 0x448:
+ device_str = "STM32F07x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x442:
+ device_str = "STM32F09x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ default:
+ snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
return ERROR_FAIL;
}
+ if (rev_str != NULL)
+ snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
+ else
+ snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
+
return ERROR_OK;
}
@@ -1307,9 +1165,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
struct stm32x_flash_bank *stm32x_info = NULL;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
@@ -1320,8 +1176,7 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1330,17 +1185,15 @@ COMMAND_HANDLER(stm32x_handle_lock_command)
if (ERROR_OK != retval)
return retval;
- if (stm32x_erase_options(bank) != ERROR_OK)
- {
+ if (stm32x_erase_options(bank) != ERROR_OK) {
command_print(CMD_CTX, "stm32x failed to erase options");
return ERROR_OK;
}
/* set readout protection */
- stm32x_info->option_bytes.RDP = 0;
+ stm32x_info->option_bytes.rdp = 0;
- if (stm32x_write_options(bank) != ERROR_OK)
- {
+ if (stm32x_write_options(bank) != ERROR_OK) {
command_print(CMD_CTX, "stm32x failed to lock device");
return ERROR_OK;
}
@@ -1355,9 +1208,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
struct target *target = NULL;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
@@ -1366,8 +1217,7 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1376,15 +1226,13 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
if (ERROR_OK != retval)
return retval;
- if (stm32x_erase_options(bank) != ERROR_OK)
- {
- command_print(CMD_CTX, "stm32x failed to unlock device");
+ if (stm32x_erase_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "stm32x failed to erase options");
return ERROR_OK;
}
- if (stm32x_write_options(bank) != ERROR_OK)
- {
- command_print(CMD_CTX, "stm32x failed to lock device");
+ if (stm32x_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "stm32x failed to unlock device");
return ERROR_OK;
}
@@ -1397,14 +1245,12 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
COMMAND_HANDLER(stm32x_handle_options_read_command)
{
- uint32_t optionbyte;
+ uint32_t optionbyte, protection;
struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
@@ -1415,8 +1261,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1428,38 +1273,38 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
if (retval != ERROR_OK)
return retval;
- command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
- command_print(CMD_CTX, "Option Byte Complement Error");
+ uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
- command_print(CMD_CTX, "Readout Protection On");
- else
- command_print(CMD_CTX, "Readout Protection Off");
+ retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
+ if (retval != ERROR_OK)
+ return retval;
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
- command_print(CMD_CTX, "Software Watchdog");
- else
- command_print(CMD_CTX, "Hardware Watchdog");
+ if (optionbyte & (1 << OPT_ERROR))
+ command_print(CMD_CTX, "option byte complement error");
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
- command_print(CMD_CTX, "Stop: No reset generated");
- else
- command_print(CMD_CTX, "Stop: Reset generated");
+ command_print(CMD_CTX, "option byte register = 0x%" PRIx32 "", optionbyte);
+ command_print(CMD_CTX, "write protection register = 0x%" PRIx32 "", protection);
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
- command_print(CMD_CTX, "Standby: No reset generated");
- else
- command_print(CMD_CTX, "Standby: Reset generated");
+ command_print(CMD_CTX, "read protection: %s",
+ (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
+
+ /* user option bytes are offset depending on variant */
+ optionbyte >>= stm32x_info->option_offset;
+
+ command_print(CMD_CTX, "watchdog: %sware",
+ (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
+
+ command_print(CMD_CTX, "stop mode: %sreset generated upon entry",
+ (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
+
+ command_print(CMD_CTX, "standby mode: %sreset generated upon entry",
+ (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
if (stm32x_info->has_dual_banks)
- {
- if (buf_get_u32((uint8_t*)&optionbyte, OPT_BFB2, 1))
- command_print(CMD_CTX, "Boot: Bank 0");
- else
- command_print(CMD_CTX, "Boot: Bank 1");
- }
+ command_print(CMD_CTX, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
+
+ command_print(CMD_CTX, "user data = 0x%02" PRIx16 "", user_data);
return ERROR_OK;
}
@@ -1468,12 +1313,10 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
{
struct target *target = NULL;
struct stm32x_flash_bank *stm32x_info = NULL;
- uint16_t optionbyte = 0xF8;
+ uint16_t optionbyte;
- if (CMD_ARGC < 4)
- {
+ if (CMD_ARGC < 2)
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
@@ -1484,8 +1327,7 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1494,70 +1336,105 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
if (ERROR_OK != retval)
return retval;
- /* REVISIT: ignores some options which we will display...
- * and doesn't insist on the specified syntax.
- */
-
- /* OPT_RDWDGSW */
- if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
- {
- optionbyte |= (1 << 0);
- }
- else /* REVISIT must be "HWWDG" then ... */
- {
- optionbyte &= ~(1 << 0);
- }
-
- /* OPT_RDRSTSTOP */
- if (strcmp(CMD_ARGV[2], "NORSTSTOP") == 0)
- {
- optionbyte |= (1 << 1);
- }
- else /* REVISIT must be "RSTSTNDBY" then ... */
- {
- optionbyte &= ~(1 << 1);
- }
-
- /* OPT_RDRSTSTDBY */
- if (strcmp(CMD_ARGV[3], "NORSTSTNDBY") == 0)
- {
- optionbyte |= (1 << 2);
- }
- else /* REVISIT must be "RSTSTOP" then ... */
- {
- optionbyte &= ~(1 << 2);
- }
+ retval = stm32x_read_options(bank);
+ if (ERROR_OK != retval)
+ return retval;
- if (CMD_ARGC > 4 && stm32x_info->has_dual_banks)
- {
- /* OPT_BFB2 */
- if (strcmp(CMD_ARGV[4], "BOOT0") == 0)
- {
- optionbyte |= (1 << 3);
- }
- else
- {
- optionbyte &= ~(1 << 3);
- }
+ /* start with current options */
+ optionbyte = stm32x_info->option_bytes.user;
+
+ /* skip over flash bank */
+ CMD_ARGC--;
+ CMD_ARGV++;
+
+ while (CMD_ARGC) {
+ if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 0);
+ else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
+ optionbyte &= ~(1 << 0);
+ else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 1);
+ else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
+ optionbyte &= ~(1 << 1);
+ else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 2);
+ else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
+ optionbyte &= ~(1 << 2);
+ else if (stm32x_info->has_dual_banks) {
+ if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 3);
+ else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
+ optionbyte &= ~(1 << 3);
+ else
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ } else
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ CMD_ARGC--;
+ CMD_ARGV++;
}
- if (stm32x_erase_options(bank) != ERROR_OK)
- {
+ if (stm32x_erase_options(bank) != ERROR_OK) {
command_print(CMD_CTX, "stm32x failed to erase options");
return ERROR_OK;
}
- stm32x_info->option_bytes.user_options = optionbyte;
+ stm32x_info->option_bytes.user = optionbyte;
- if (stm32x_write_options(bank) != ERROR_OK)
- {
+ if (stm32x_write_options(bank) != ERROR_OK) {
command_print(CMD_CTX, "stm32x failed to write options");
return ERROR_OK;
}
command_print(CMD_CTX, "stm32x write options complete.\n"
- "INFO: a reset or power cycle is required "
- "for the new settings to take effect.");
+ "INFO: %spower cycle is required "
+ "for the new settings to take effect.",
+ stm32x_info->can_load_options
+ ? "'stm32f1x options_load' command or " : "");
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(stm32x_handle_options_load_command)
+{
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
+
+ if (!stm32x_info->can_load_options) {
+ LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
+ "required instead.");
+ return ERROR_FAIL;
+ }
+
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = stm32x_check_operation_supported(bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ /* unlock option flash registers */
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* force re-load of option bytes - generates software reset */
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
+ if (retval != ERROR_OK)
+ return retval;
return ERROR_OK;
}
@@ -1566,8 +1443,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
{
struct target *target = bank->target;
- if (target->state != TARGET_HALTED)
- {
+ if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1584,11 +1460,12 @@ static int stm32x_mass_erase(struct flash_bank *bank)
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_STRT);
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
+ FLASH_MER | FLASH_STRT);
if (retval != ERROR_OK)
return retval;
- retval = stm32x_wait_status_busy(bank, 100);
+ retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
if (retval != ERROR_OK)
return retval;
@@ -1604,9 +1481,7 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
int i;
if (CMD_ARGC < 1)
- {
return ERROR_COMMAND_SYNTAX_ERROR;
- }
struct flash_bank *bank;
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
@@ -1614,20 +1489,14 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
return retval;
retval = stm32x_mass_erase(bank);
- if (retval == ERROR_OK)
- {
+ if (retval == ERROR_OK) {
/* set all sectors as erased */
for (i = 0; i < bank->num_sectors; i++)
- {
bank->sectors[i].is_erased = 1;
- }
command_print(CMD_CTX, "stm32x mass erase complete");
- }
- else
- {
+ } else
command_print(CMD_CTX, "stm32x mass erase failed");
- }
return retval;
}
@@ -1659,7 +1528,7 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.handler = stm32x_handle_options_read_command,
.mode = COMMAND_EXEC,
.usage = "bank_id",
- .help = "Read and display device option byte.",
+ .help = "Read and display device option bytes.",
},
{
.name = "options_write",
@@ -1668,7 +1537,14 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.usage = "bank_id ('SWWDG'|'HWWDG') "
"('RSTSTNDBY'|'NORSTSTNDBY') "
"('RSTSTOP'|'NORSTSTOP')",
- .help = "Replace bits in device option byte.",
+ .help = "Replace bits in device option bytes.",
+ },
+ {
+ .name = "options_load",
+ .handler = stm32x_handle_options_load_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Force re-load of device option bytes.",
},
COMMAND_REGISTRATION_DONE
};
@@ -1694,7 +1570,8 @@ struct flash_driver stm32f1x_flash = {
.read = default_flash_read,
.probe = stm32x_probe,
.auto_probe = stm32x_auto_probe,
- .erase_check = default_flash_mem_blank_check,
+ .erase_check = default_flash_blank_check,
.protect_check = stm32x_protect_check,
.info = get_stm32x_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};