X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fpic32mx.c;h=2b27ec5b8bd5cddbc812e0dfa0867c1a69f81baf;hp=d2289b297ffabec997f5e9bf496526e7178fa585;hb=4831236af4a49c315b79923ba31b80243969a901;hpb=a8880f0b5ab7f5c9d4d3b031fd487caac766b99f

diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index d2289b297f..2b27ec5b8b 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -21,44 +21,164 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
 
-#include "pic32mx.h"
+#include <jtag/jtag.h>
+#include "imp.h"
+#include <target/algorithm.h>
 #include <target/mips32.h>
+#include <target/mips_m4k.h>
 
+#define PIC32MX_MANUF_ID	0x029
 
-static
-struct pic32mx_devs_s {
-	uint8_t	devid;
-	char	*name;
-	uint32_t	pfm_size;
-} pic32mx_devs[] = {
-	{ 0x78, "460F512L USB", 512 },
-	{ 0x74, "460F256L USB", 256 },
-	{ 0x6D, "440F128L USB", 128 },
-	{ 0x56, "440F512H USB", 512 },
-	{ 0x52, "440F256H USB", 256 },
-	{ 0x4D, "440F128H USB", 128 },
-	{ 0x42, "420F032H USB",  32 },
-	{ 0x38, "360F512L",     512 },
-	{ 0x34, "360F256L",     256 },
-	{ 0x2D, "340F128L",     128 },
-	{ 0x2A, "320F128L",     128 },
-	{ 0x16, "340F512H",     512 },
-	{ 0x12, "340F256H",     256 },
-	{ 0x0D, "340F128H",     128 },
-	{ 0x0A, "320F128H",     128 },
-	{ 0x06, "320F064H",      64 },
-	{ 0x02, "320F032H",      32 },
-	{ 0x00, NULL, 0 }
+/* pic32mx memory locations */
+
+#define PIC32MX_PHYS_RAM			0x00000000
+#define PIC32MX_PHYS_PGM_FLASH		0x1D000000
+#define PIC32MX_PHYS_PERIPHERALS	0x1F800000
+#define PIC32MX_PHYS_BOOT_FLASH		0x1FC00000
+
+/*
+ * Translate Virtual and Physical addresses.
+ * Note: These macros only work for KSEG0/KSEG1 addresses.
+ */
+
+#define Virt2Phys(v)	((v) & 0x1FFFFFFF)
+
+/* pic32mx configuration register locations */
+
+#define PIC32MX_DEVCFG0_1_2	0xBFC00BFC
+#define PIC32MX_DEVCFG0		0xBFC02FFC
+#define PIC32MX_DEVCFG1		0xBFC02FF8
+#define PIC32MX_DEVCFG2		0xBFC02FF4
+#define PIC32MX_DEVCFG3		0xBFC02FF0
+#define PIC32MX_DEVID		0xBF80F220
+
+#define PIC32MX_BMXPFMSZ	0xBF882060
+#define PIC32MX_BMXBOOTSZ	0xBF882070
+#define PIC32MX_BMXDRMSZ	0xBF882040
+
+/* pic32mx flash controller register locations */
+
+#define PIC32MX_NVMCON		0xBF80F400
+#define PIC32MX_NVMCONCLR	0xBF80F404
+#define PIC32MX_NVMCONSET	0xBF80F408
+#define PIC32MX_NVMCONINV	0xBF80F40C
+#define NVMCON_NVMWR		(1 << 15)
+#define NVMCON_NVMWREN		(1 << 14)
+#define NVMCON_NVMERR		(1 << 13)
+#define NVMCON_LVDERR		(1 << 12)
+#define NVMCON_LVDSTAT		(1 << 11)
+#define NVMCON_OP_PFM_ERASE		0x5
+#define NVMCON_OP_PAGE_ERASE	0x4
+#define NVMCON_OP_ROW_PROG		0x3
+#define NVMCON_OP_WORD_PROG		0x1
+#define NVMCON_OP_NOP			0x0
+
+#define PIC32MX_NVMKEY		0xBF80F410
+#define PIC32MX_NVMADDR		0xBF80F420
+#define PIC32MX_NVMADDRCLR	0xBF80F424
+#define PIC32MX_NVMADDRSET	0xBF80F428
+#define PIC32MX_NVMADDRINV	0xBF80F42C
+#define PIC32MX_NVMDATA		0xBF80F430
+#define PIC32MX_NVMSRCADDR	0xBF80F440
+
+/* flash unlock keys */
+
+#define NVMKEY1			0xAA996655
+#define NVMKEY2			0x556699AA
+
+#define MX_1_2			1	/* PIC32mx1xx/2xx */
+
+struct pic32mx_flash_bank {
+	int probed;
+	int dev_type;		/* Default 0. 1 for Pic32MX1XX/2XX variant */
 };
 
-static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr);
-static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word);
+/*
+ * DEVID values as per PIC32MX Flash Programming Specification Rev J
+ */
+
+static const struct pic32mx_devs_s {
+	uint32_t devid;
+	const char *name;
+} pic32mx_devs[] = {
+	{0x04A07053, "110F016B"},
+	{0x04A09053, "110F016C"},
+	{0x04A0B053, "110F016D"},
+	{0x04A06053, "120F032B"},
+	{0x04A08053, "120F032C"},
+	{0x04A0A053, "120F032D"},
+	{0x04D07053, "130F064B"},
+	{0x04D09053, "130F064C"},
+	{0x04D0B053, "130F064D"},
+	{0x04D06053, "150F128B"},
+	{0x04D08053, "150F128C"},
+	{0x04D0A053, "150F128D"},
+	{0x04A01053, "210F016B"},
+	{0x04A03053, "210F016C"},
+	{0x04A05053, "210F016D"},
+	{0x04A00053, "220F032B"},
+	{0x04A02053, "220F032C"},
+	{0x04A04053, "220F032D"},
+	{0x04D01053, "230F064B"},
+	{0x04D03053, "230F064C"},
+	{0x04D05053, "230F064D"},
+	{0x04D00053, "250F128B"},
+	{0x04D02053, "250F128C"},
+	{0x04D04053, "250F128D"},
+	{0x00938053, "360F512L"},
+	{0x00934053, "360F256L"},
+	{0x0092D053, "340F128L"},
+	{0x0092A053, "320F128L"},
+	{0x00916053, "340F512H"},
+	{0x00912053, "340F256H"},
+	{0x0090D053, "340F128H"},
+	{0x0090A053, "320F128H"},
+	{0x00906053, "320F064H"},
+	{0x00902053, "320F032H"},
+	{0x00978053, "460F512L"},
+	{0x00974053, "460F256L"},
+	{0x0096D053, "440F128L"},
+	{0x00952053, "440F256H"},
+	{0x00956053, "440F512H"},
+	{0x0094D053, "440F128H"},
+	{0x00942053, "420F032H"},
+	{0x04307053, "795F512L"},
+	{0x0430E053, "795F512H"},
+	{0x04306053, "775F512L"},
+	{0x0430D053, "775F512H"},
+	{0x04312053, "775F256L"},
+	{0x04303053, "775F256H"},
+	{0x04417053, "764F128L"},
+	{0x0440B053, "764F128H"},
+	{0x04341053, "695F512L"},
+	{0x04325053, "695F512H"},
+	{0x04311053, "675F512L"},
+	{0x0430C053, "675F512H"},
+	{0x04305053, "675F256L"},
+	{0x0430B053, "675F256H"},
+	{0x04413053, "664F128L"},
+	{0x04407053, "664F128H"},
+	{0x04411053, "664F064L"},
+	{0x04405053, "664F064H"},
+	{0x0430F053, "575F512L"},
+	{0x04309053, "575F512H"},
+	{0x04333053, "575F256L"},
+	{0x04317053, "575F256H"},
+	{0x0440F053, "564F128L"},
+	{0x04403053, "564F128H"},
+	{0x0440D053, "564F064L"},
+	{0x04401053, "564F064H"},
+	{0x04400053, "534F064H"},
+	{0x0440C053, "534F064L"},
+	{0x00000000, NULL}
+};
 
 /* flash bank pic32mx <base> <size> 0 0 <target#>
  */
@@ -67,16 +187,13 @@ FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
 	struct pic32mx_flash_bank *pic32mx_info;
 
 	if (CMD_ARGC < 6)
-	{
-		LOG_WARNING("incomplete flash_bank pic32mx configuration");
-		return ERROR_FLASH_BANK_INVALID;
-	}
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
 	bank->driver_priv = pic32mx_info;
 
-	pic32mx_info->write_algorithm = NULL;
 	pic32mx_info->probed = 0;
+	pic32mx_info->dev_type = 0;
 
 	return ERROR_OK;
 }
@@ -96,8 +213,7 @@ static uint32_t pic32mx_wait_status_busy(struct flash_bank *bank, int timeout)
 	uint32_t status;
 
 	/* wait for busy to clear */
-	while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
-	{
+	while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0)) {
 		LOG_DEBUG("status: 0x%" PRIx32, status);
 		alive_sleep(1);
 	}
@@ -132,29 +248,40 @@ static int pic32mx_nvm_exec(struct flash_bank *bank, uint32_t op, uint32_t timeo
 static int pic32mx_protect_check(struct flash_bank *bank)
 {
 	struct target *target = bank->target;
+	struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
 
+	uint32_t config0_address;
 	uint32_t devcfg0;
 	int s;
 	int num_pages;
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
+	if (pic32mx_info->dev_type == MX_1_2)
+		config0_address = PIC32MX_DEVCFG0_1_2;
+	else
+		config0_address = PIC32MX_DEVCFG0;
+
+	target_read_u32(target, config0_address, &devcfg0);
+
 	if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
-		num_pages = 0xffff;  /* All pages protected */
-	else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
-	{
+		num_pages = 0xffff;			/* All pages protected */
+	else if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
 		if (devcfg0 & (1 << 24))
-			num_pages = 0;       /* All pages unprotected */
+			num_pages = 0;			/* All pages unprotected */
 		else
-			num_pages = 0xffff;  /* All pages protected */
+			num_pages = 0xffff;		/* All pages protected */
+	} else {
+		/* pgm flash */
+		if (pic32mx_info->dev_type == MX_1_2)
+			num_pages = (~devcfg0 >> 10) & 0x3f;
+		else
+			num_pages = (~devcfg0 >> 12) & 0xff;
 	}
-	else /* pgm flash */
-		num_pages = (~devcfg0 >> 12) & 0xff;
+
 	for (s = 0; s < bank->num_sectors && s < num_pages; s++)
 		bank->sectors[s].is_protected = 1;
 	for (; s < bank->num_sectors; s++)
@@ -169,14 +296,15 @@ static int pic32mx_erase(struct flash_bank *bank, int first, int last)
 	int i;
 	uint32_t status;
 
-	if (bank->target->state != TARGET_HALTED)
-	{
+	if (bank->target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
-	{
+	if ((first == 0) && (last == (bank->num_sectors - 1))
+		&& (Virt2Phys(bank->base) == PIC32MX_PHYS_PGM_FLASH)) {
+		/* this will only erase the Program Flash (PFM), not the Boot Flash (BFM)
+		 * we need to use the MTAP to perform a full erase */
 		LOG_DEBUG("Erasing entire program flash");
 		status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
 		if (status & NVMCON_NVMERR)
@@ -186,12 +314,8 @@ static int pic32mx_erase(struct flash_bank *bank, int first, int last)
 		return ERROR_OK;
 	}
 
-	for (i = first; i <= last; i++)
-	{
-		if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
-			target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(bank->base + bank->sectors[i].offset));
-		else
-			target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(bank->base + bank->sectors[i].offset));
+	for (i = first; i <= last; i++) {
+		target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(bank->base + bank->sectors[i].offset));
 
 		status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
 
@@ -207,223 +331,233 @@ static int pic32mx_erase(struct flash_bank *bank, int first, int last)
 
 static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
 {
-	struct pic32mx_flash_bank *pic32mx_info = NULL;
 	struct target *target = bank->target;
-#if 0
-	uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
-	int i, reg, bit;
-	int status;
-	uint32_t protection;
-#endif
 
-	pic32mx_info = bank->driver_priv;
-
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-#if 0
-	if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))
-	{
-		LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);
-		return ERROR_FLASH_SECTOR_INVALID;
-	}
-
-	/* medium density - each bit refers to a 4bank protection
-	 * high density - each bit refers to a 2bank protection */
-	target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
-
-	prot_reg[0] = (uint16_t)protection;
-	prot_reg[1] = (uint16_t)(protection >> 8);
-	prot_reg[2] = (uint16_t)(protection >> 16);
-	prot_reg[3] = (uint16_t)(protection >> 24);
-
-	if (pic32mx_info->ppage_size == 2)
-	{
-		/* high density flash */
-
-		/* bit 7 controls sector 62 - 255 protection */
-		if (last > 61)
-		{
-			if (set)
-				prot_reg[3] &= ~(1 << 7);
-			else
-				prot_reg[3] |= (1 << 7);
-		}
-
-		if (first > 61)
-			first = 62;
-		if (last > 61)
-			last = 61;
-
-		for (i = first; i <= last; i++)
-		{
-			reg = (i / pic32mx_info->ppage_size) / 8;
-			bit = (i / pic32mx_info->ppage_size) - (reg * 8);
-
-			if (set)
-				prot_reg[reg] &= ~(1 << bit);
-			else
-				prot_reg[reg] |= (1 << bit);
-		}
-	}
-	else
-	{
-		/* medium density flash */
-		for (i = first; i <= last; i++)
-		{
-			reg = (i / pic32mx_info->ppage_size) / 8;
-			bit = (i / pic32mx_info->ppage_size) - (reg * 8);
-
-			if (set)
-				prot_reg[reg] &= ~(1 << bit);
-			else
-				prot_reg[reg] |= (1 << bit);
-		}
-	}
-
-	if ((status = pic32mx_erase_options(bank)) != ERROR_OK)
-		return status;
-
-	pic32mx_info->option_bytes.protection[0] = prot_reg[0];
-	pic32mx_info->option_bytes.protection[1] = prot_reg[1];
-	pic32mx_info->option_bytes.protection[2] = prot_reg[2];
-	pic32mx_info->option_bytes.protection[3] = prot_reg[3];
-
-	return pic32mx_write_options(bank);
-#else
 	return ERROR_OK;
-#endif
 }
 
-static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+/* see contib/loaders/flash/pic32mx.s for src */
+
+static uint32_t pic32mx_flash_write_code[] = {
+					/* write: */
+	0x3C08AA99,		/* lui $t0, 0xaa99 */
+	0x35086655,		/* ori $t0, 0x6655 */
+	0x3C095566,		/* lui $t1, 0x5566 */
+	0x352999AA,		/* ori $t1, 0x99aa */
+	0x3C0ABF80,		/* lui $t2, 0xbf80 */
+	0x354AF400,		/* ori $t2, 0xf400 */
+	0x340B4003,		/* ori $t3, $zero, 0x4003 */
+	0x340C8000,		/* ori $t4, $zero, 0x8000 */
+					/* write_row: */
+	0x2CD30080,		/* sltiu $s3, $a2, 128 */
+	0x16600008,		/* bne $s3, $zero, write_word */
+	0x340D4000,		/* ori $t5, $zero, 0x4000 */
+	0xAD450020,		/* sw $a1, 32($t2) */
+	0xAD440040,		/* sw $a0, 64($t2) */
+	0x04110016,		/* bal progflash */
+	0x24840200,		/* addiu $a0, $a0, 512 */
+	0x24A50200,		/* addiu $a1, $a1, 512 */
+	0x1000FFF7,		/* beq $zero, $zero, write_row */
+	0x24C6FF80,		/* addiu $a2, $a2, -128 */
+					/* write_word: */
+	0x3C15A000,		/* lui $s5, 0xa000 */
+	0x36B50000,		/* ori $s5, $s5, 0x0 */
+	0x00952025,		/* or $a0, $a0, $s5 */
+	0x10000008,		/* beq $zero, $zero, next_word */
+	0x340B4001,		/* ori $t3, $zero, 0x4001 */
+					/* prog_word: */
+	0x8C940000,		/* lw $s4, 0($a0) */
+	0xAD540030,		/* sw $s4, 48($t2) */
+	0xAD450020,		/* sw $a1, 32($t2) */
+	0x04110009,		/* bal progflash */
+	0x24840004,		/* addiu $a0, $a0, 4 */
+	0x24A50004,		/* addiu $a1, $a1, 4 */
+	0x24C6FFFF,		/* addiu $a2, $a2, -1 */
+					/* next_word: */
+	0x14C0FFF8,		/* bne $a2, $zero, prog_word */
+	0x00000000,		/* nop */
+					/* done: */
+	0x10000002,		/* beq $zero, $zero, exit */
+	0x24040000,		/* addiu $a0, $zero, 0 */
+					/* error: */
+	0x26240000,		/* addiu $a0, $s1, 0 */
+					/* exit: */
+	0x7000003F,		/* sdbbp */
+					/* progflash: */
+	0xAD4B0000,		/* sw $t3, 0($t2) */
+	0xAD480010,		/* sw $t0, 16($t2) */
+	0xAD490010,		/* sw $t1, 16($t2) */
+	0xAD4C0008,		/* sw $t4, 8($t2) */
+					/* waitflash: */
+	0x8D500000,		/* lw $s0, 0($t2) */
+	0x020C8024,		/* and $s0, $s0, $t4 */
+	0x1600FFFD,		/* bne $s0, $zero, waitflash */
+	0x00000000,		/* nop */
+	0x00000000,		/* nop */
+	0x00000000,		/* nop */
+	0x00000000,		/* nop */
+	0x00000000,		/* nop */
+	0x8D510000,		/* lw $s1, 0($t2) */
+	0x30113000,		/* andi $s1, $zero, 0x3000 */
+	0x1620FFEF,		/* bne $s1, $zero, error */
+	0xAD4D0004,		/* sw $t5, 4($t2) */
+	0x03E00008,		/* jr $ra */
+	0x00000000		/* nop */
+};
+
+static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer,
+		uint32_t offset, uint32_t count)
 {
 	struct target *target = bank->target;
-	uint32_t buffer_size = 512;
+	uint32_t buffer_size = 16384;
+	struct working_area *write_algorithm;
 	struct working_area *source;
 	uint32_t address = bank->base + offset;
+	struct reg_param reg_params[3];
+	uint32_t row_size;
 	int retval = ERROR_OK;
-#if 0
+
 	struct pic32mx_flash_bank *pic32mx_info = bank->driver_priv;
-	struct armv7m_algorithm armv7m_info;
-
-	uint8_t pic32mx_flash_write_code[] = {
-									/* write: */
-		0xDF, 0xF8, 0x24, 0x40,		/* ldr	r4, PIC32MX_FLASH_CR */
-		0x09, 0x4D,					/* ldr	r5, PIC32MX_FLASH_SR */
-		0x4F, 0xF0, 0x01, 0x03,		/* mov	r3, #1 */
-		0x23, 0x60,					/* str	r3, [r4, #0] */
-		0x30, 0xF8, 0x02, 0x3B,		/* ldrh r3, [r0], #2 */
-		0x21, 0xF8, 0x02, 0x3B,		/* strh r3, [r1], #2 */
-									/* busy: */
-		0x2B, 0x68,					/* ldr 	r3, [r5, #0] */
-		0x13, 0xF0, 0x01, 0x0F,		/* tst 	r3, #0x01 */
-		0xFB, 0xD0,					/* beq 	busy */
-		0x13, 0xF0, 0x14, 0x0F,		/* tst	r3, #0x14 */
-		0x01, 0xD1,					/* bne	exit */
-		0x01, 0x3A,					/* subs	r2, r2, #1 */
-		0xED, 0xD1,					/* bne	write */
-									/* exit: */
-		0xFE, 0xE7,					/* b exit */
-		0x10, 0x20, 0x02, 0x40,		/* PIC32MX_FLASH_CR:	.word 0x40022010 */
-		0x0C, 0x20, 0x02, 0x40		/* PIC32MX_FLASH_SR:	.word 0x4002200C */
-	};
+	struct mips32_algorithm mips32_info;
 
 	/* flash write code */
-	if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)
-	{
+	if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code),
+			&write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	};
 
-	if ((retval = target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code)) != ERROR_OK)
+	/* Change values for counters and row size, depending on variant */
+	if (pic32mx_info->dev_type == MX_1_2) {
+		/* 128 byte row */
+		pic32mx_flash_write_code[8] = 0x2CD30020;
+		pic32mx_flash_write_code[14] = 0x24840080;
+		pic32mx_flash_write_code[15] = 0x24A50080;
+		pic32mx_flash_write_code[17] = 0x24C6FFE0;
+		row_size = 128;
+	} else {
+		/* 512 byte row */
+		pic32mx_flash_write_code[8] = 0x2CD30080;
+		pic32mx_flash_write_code[14] = 0x24840200;
+		pic32mx_flash_write_code[15] = 0x24A50200;
+		pic32mx_flash_write_code[17] = 0x24C6FF80;
+		row_size = 512;
+	}
+
+	uint8_t code[sizeof(pic32mx_flash_write_code)];
+	target_buffer_set_u32_array(target, code, ARRAY_SIZE(pic32mx_flash_write_code),
+			pic32mx_flash_write_code);
+	retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
+	if (retval != ERROR_OK)
 		return retval;
-#endif
 
 	/* memory buffer */
-	if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
-	{
-#if 0
-		/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
-		if (pic32mx_info->write_algorithm)
-			target_free_working_area(target, pic32mx_info->write_algorithm);
-#endif
-
-		LOG_WARNING("no large enough working area available, can't do block memory writes");
-		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+		buffer_size /= 2;
+		if (buffer_size <= 256) {
+			/* we already allocated the writing code, but failed to get a
+			 * buffer, free the algorithm */
+			target_free_working_area(target, write_algorithm);
+
+			LOG_WARNING("no large enough working area available, can't do block memory writes");
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
 	}
 
-	while (count >= buffer_size/4)
-	{
+	mips32_info.common_magic = MIPS32_COMMON_MAGIC;
+	mips32_info.isa_mode = MIPS32_ISA_MIPS32;
+
+	init_reg_param(&reg_params[0], "a0", 32, PARAM_IN_OUT);
+	init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT);
+	init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT);
+
+	int row_offset = offset % row_size;
+	uint8_t *new_buffer = NULL;
+	if (row_offset && (count >= (row_size / 4))) {
+		new_buffer = malloc(buffer_size);
+		if (new_buffer == NULL) {
+			LOG_ERROR("Out of memory");
+			return ERROR_FAIL;
+		}
+		memset(new_buffer,  0xff, row_offset);
+		address -= row_offset;
+	} else
+		row_offset = 0;
+
+	while (count > 0) {
 		uint32_t status;
+		uint32_t thisrun_count;
 
-		if ((retval = target_write_buffer(target, source->address, buffer_size, buffer)) != ERROR_OK) {
-			LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
-			break;
+		if (row_offset) {
+			thisrun_count = (count > ((buffer_size - row_offset) / 4)) ?
+				((buffer_size - row_offset) / 4) : count;
+
+			memcpy(new_buffer + row_offset, buffer, thisrun_count * 4);
+
+			retval = target_write_buffer(target, source->address,
+				row_offset + thisrun_count * 4, new_buffer);
+			if (retval != ERROR_OK)
+				break;
+		} else {
+			thisrun_count = (count > (buffer_size / 4)) ?
+					(buffer_size / 4) : count;
+
+			retval = target_write_buffer(target, source->address,
+					thisrun_count * 4, buffer);
+			if (retval != ERROR_OK)
+				break;
 		}
 
-#if 0
-		buf_set_u32(reg_params[0].value, 0, 32, source->address);
-		buf_set_u32(reg_params[1].value, 0, 32, address);
-		buf_set_u32(reg_params[2].value, 0, 32, buffer_size/4);
+		buf_set_u32(reg_params[0].value, 0, 32, Virt2Phys(source->address));
+		buf_set_u32(reg_params[1].value, 0, 32, Virt2Phys(address));
+		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count + row_offset / 4);
 
-		if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
-				pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
-		{
+		retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+				write_algorithm->address,
+				0, 10000, &mips32_info);
+		if (retval != ERROR_OK) {
 			LOG_ERROR("error executing pic32mx flash write algorithm");
 			retval = ERROR_FLASH_OPERATION_FAILED;
 			break;
 		}
 
-		if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
-		{
-			retval = ERROR_FLASH_OPERATION_FAILED;
-			break;
-		}
-#endif
-		status = pic32mx_write_row(bank, address, source->address);
+		status = buf_get_u32(reg_params[0].value, 0, 32);
+
 		if (status & NVMCON_NVMERR) {
 			LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
 			retval = ERROR_FLASH_OPERATION_FAILED;
 			break;
 		}
+
 		if (status & NVMCON_LVDERR) {
 			LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
 			retval = ERROR_FLASH_OPERATION_FAILED;
 			break;
 		}
 
-		buffer  += buffer_size;
-		address += buffer_size;
-		count   -= buffer_size/4;
+		buffer += thisrun_count * 4;
+		address += thisrun_count * 4;
+		count -= thisrun_count;
+		if (row_offset) {
+			address += row_offset;
+			row_offset = 0;
+		}
 	}
 
 	target_free_working_area(target, source);
+	target_free_working_area(target, write_algorithm);
 
-	while (count > 0)
-	{
-		uint32_t value;
-		memcpy(&value, buffer, sizeof(uint32_t));
-
-		uint32_t status = pic32mx_write_word(bank, address, value);
-		if (status & NVMCON_NVMERR) {
-			LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
-			retval = ERROR_FLASH_OPERATION_FAILED;
-			break;
-		}
-		if (status & NVMCON_LVDERR) {
-			LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
-			retval = ERROR_FLASH_OPERATION_FAILED;
-			break;
-		}
-
-		buffer  += 4;
-		address += 4;
-		count--;
-	}
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
 
+	if (new_buffer != NULL)
+		free(new_buffer);
 	return retval;
 }
 
@@ -431,36 +565,12 @@ static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_
 {
 	struct target *target = bank->target;
 
-	if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
-		target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
-	else
-		target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
+	target_write_u32(target, PIC32MX_NVMADDR, Virt2Phys(address));
 	target_write_u32(target, PIC32MX_NVMDATA, word);
 
 	return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
 }
 
-/*
- * Write a 128 word (512 byte) row to flash address from RAM srcaddr.
- */
-static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr)
-{
-	struct target *target = bank->target;
-
-	LOG_DEBUG("addr: 0x%08" PRIx32 " srcaddr: 0x%08" PRIx32 "", address, srcaddr);
-
-	if (address >= PIC32MX_KSEG1_PGM_FLASH)
-		target_write_u32(target, PIC32MX_NVMADDR,    KS1Virt2Phys(address));
-	else
-		target_write_u32(target, PIC32MX_NVMADDR,    KS0Virt2Phys(address));
-	if (srcaddr >= PIC32MX_KSEG1_RAM)
-		target_write_u32(target, PIC32MX_NVMSRCADDR, KS1Virt2Phys(srcaddr));
-	else
-		target_write_u32(target, PIC32MX_NVMSRCADDR, KS0Virt2Phys(srcaddr));
-
-	return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
-}
-
 static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 {
 	uint32_t words_remaining = (count / 4);
@@ -470,70 +580,75 @@ static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offs
 	uint32_t status;
 	int retval;
 
-	if (bank->target->state != TARGET_HALTED)
-	{
+	if (bank->target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	if (offset & 0x3)
-	{
+	LOG_DEBUG("writing to flash at address 0x%08" PRIx32 " at offset 0x%8.8" PRIx32
+			" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
+
+	if (offset & 0x3) {
 		LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
 		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 	}
 
 	/* multiple words (4-byte) to be programmed? */
-	if (words_remaining > 0)
-	{
+	if (words_remaining > 0) {
 		/* try using a block write */
-		if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
-		{
-			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
-			{
+		retval = pic32mx_write_block(bank, buffer, offset, words_remaining);
+		if (retval != ERROR_OK) {
+			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 				/* if block write failed (no sufficient working area),
 				 * we use normal (slow) single dword accesses */
 				LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+			} else if (retval == ERROR_FLASH_OPERATION_FAILED) {
+				LOG_ERROR("flash writing failed");
+				return retval;
 			}
-			else if (retval == ERROR_FLASH_OPERATION_FAILED)
-			{
-				LOG_ERROR("flash writing failed with error code: 0x%x", retval);
-				return ERROR_FLASH_OPERATION_FAILED;
-			}
-		}
-		else
-		{
+		} else {
 			buffer += words_remaining * 4;
 			address += words_remaining * 4;
 			words_remaining = 0;
 		}
 	}
 
-	while (words_remaining > 0)
-	{
+	while (words_remaining > 0) {
 		uint32_t value;
 		memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
 
 		status = pic32mx_write_word(bank, address, value);
-		if (status & NVMCON_NVMERR)
+
+		if (status & NVMCON_NVMERR) {
+			LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
 			return ERROR_FLASH_OPERATION_FAILED;
-		if (status & NVMCON_LVDERR)
+		}
+
+		if (status & NVMCON_LVDERR) {
+			LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
 			return ERROR_FLASH_OPERATION_FAILED;
+		}
 
 		bytes_written += 4;
 		words_remaining--;
 		address += 4;
 	}
 
-	if (bytes_remaining)
-	{
+	if (bytes_remaining) {
 		uint32_t value = 0xffffffff;
 		memcpy(&value, buffer + bytes_written, bytes_remaining);
 
 		status = pic32mx_write_word(bank, address, value);
-		if (status & NVMCON_NVMERR)
+
+		if (status & NVMCON_NVMERR) {
+			LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
 			return ERROR_FLASH_OPERATION_FAILED;
-		if (status & NVMCON_LVDERR)
+		}
+
+		if (status & NVMCON_LVDERR) {
+			LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
 			return ERROR_FLASH_OPERATION_FAILED;
+		}
 	}
 
 	return ERROR_OK;
@@ -546,71 +661,83 @@ static int pic32mx_probe(struct flash_bank *bank)
 	struct mips32_common *mips32 = target->arch_info;
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 	int i;
-	uint16_t num_pages = 0;
+	uint32_t num_pages = 0;
 	uint32_t device_id;
 	int page_size;
 
 	pic32mx_info->probed = 0;
 
 	device_id = ejtag_info->idcode;
-	LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
+	LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
 			  device_id,
-			  (unsigned)((device_id >> 1)&0x7ff),
-			  (unsigned)((device_id >> 12)&0xff),
-			  (unsigned)((device_id >> 20)&0xfff));
+			  (unsigned)((device_id >> 1) & 0x7ff),
+			  (unsigned)((device_id >> 12) & 0xffff),
+			  (unsigned)((device_id >> 28) & 0xf));
 
-	if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
+	if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
 		LOG_WARNING("Cannot identify target as a PIC32MX family.");
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 
-	page_size = 4096;
-	if (bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {
-		/* 0xBFC00000: Boot flash size fixed at 12k */
-		num_pages = 12;
-	} else {
-		/* 0xBD000000: Program flash size varies with device */
-		for (i = 0; pic32mx_devs[i].name != NULL; i++)
-			if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
-				num_pages = pic32mx_devs[i].pfm_size;
-				break;
-			}
-		if (pic32mx_devs[i].name == NULL) {
-			LOG_WARNING("Cannot identify target as a PIC32MX family.");
-			return ERROR_FLASH_OPERATION_FAILED;
+	/* Check for PIC32mx1xx/2xx */
+	for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+		if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
+			if ((*(pic32mx_devs[i].name) == '1') || (*(pic32mx_devs[i].name) == '2'))
+				pic32mx_info->dev_type = MX_1_2;
+			break;
 		}
 	}
 
+	if (pic32mx_info->dev_type == MX_1_2)
+		page_size = 1024;
+	else
+		page_size = 4096;
+
+
+	if (Virt2Phys(bank->base) == PIC32MX_PHYS_BOOT_FLASH) {
+		/* 0x1FC00000: Boot flash size */
 #if 0
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
+		/* for some reason this register returns 8k for the boot bank size
+		 * this does not match the docs, so for now set the boot bank at a
+		 * fixed 12k */
+		if (target_read_u32(target, PIC32MX_BMXBOOTSZ, &num_pages) != ERROR_OK) {
+			LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 12k flash");
+			num_pages = (12 * 1024);
+		}
+#else
+		/* fixed 12k boot bank - see comments above */
+		if (pic32mx_info->dev_type == MX_1_2)
+			num_pages = (3 * 1024);
+		else
+			num_pages = (12 * 1024);
+#endif
+	} else {
+		/* read the flash size from the device */
+		if (target_read_u32(target, PIC32MX_BMXPFMSZ, &num_pages) != ERROR_OK) {
+			if (pic32mx_info->dev_type == MX_1_2) {
+				LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 32k flash");
+				num_pages = (32 * 1024);
+			} else {
+				LOG_WARNING("PIC32MX flash size failed, probe inaccurate - assuming 512k flash");
+				num_pages = (512 * 1024);
+			}
+		}
 	}
 
-	/* get flash size from target */
-	if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
-	{
-		/* failed reading flash size, default to max target family */
-		num_pages = 0xffff;
-	}
-#endif
+	LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
 
-	LOG_INFO("flash size = %dkbytes", num_pages);
+	if (bank->sectors) {
+		free(bank->sectors);
+		bank->sectors = NULL;
+	}
 
 	/* calculate numbers of pages */
-	num_pages /= (page_size / 1024);
-
-	if (bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;
-	if (bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;
+	num_pages /= page_size;
 	bank->size = (num_pages * page_size);
 	bank->num_sectors = num_pages;
-	bank->chip_width = 4;
-	bank->bus_width  = 4;
 	bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
 
-	for (i = 0; i < num_pages; i++)
-	{
+	for (i = 0; i < (int)num_pages; i++) {
 		bank->sectors[i].offset = i * page_size;
 		bank->sectors[i].size = page_size;
 		bank->sectors[i].is_erased = -1;
@@ -630,13 +757,6 @@ static int pic32mx_auto_probe(struct flash_bank *bank)
 	return pic32mx_probe(bank);
 }
 
-#if 0
-COMMAND_HANDLER(pic32mx_handle_part_id_command)
-{
-	return ERROR_OK;
-}
-#endif
-
 static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
 {
 	struct target *target = bank->target;
@@ -647,86 +767,79 @@ static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
 
 	device_id = ejtag_info->idcode;
 
-	if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
+	if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
 		snprintf(buf, buf_size,
 				 "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
-				 (unsigned)((device_id >> 1)&0x7ff),
+				 (unsigned)((device_id >> 1) & 0x7ff),
 				 PIC32MX_MANUF_ID);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
-	for (i = 0; pic32mx_devs[i].name != NULL; i++)
-		if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
+
+	for (i = 0; pic32mx_devs[i].name != NULL; i++) {
+		if (pic32mx_devs[i].devid == (device_id & 0x0fffffff)) {
 			printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
 			break;
 		}
-	if (pic32mx_devs[i].name == NULL) {
-		snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");
-		return ERROR_FLASH_OPERATION_FAILED;
 	}
+
+	if (pic32mx_devs[i].name == NULL)
+		printed = snprintf(buf, buf_size, "Unknown");
+
 	buf += printed;
 	buf_size -= printed;
-	printed = snprintf(buf, buf_size, "  Ver: 0x%03x",
-					   (unsigned)((device_id >> 20)&0xfff));
+	snprintf(buf, buf_size, " Ver: 0x%02x",
+			(unsigned)((device_id >> 28) & 0xf));
 
 	return ERROR_OK;
 }
 
-#if 0
-COMMAND_HANDLER(pic32mx_handle_lock_command)
+COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
 {
-	struct target *target = NULL;
-	struct pic32mx_flash_bank *pic32mx_info = NULL;
+	uint32_t address, value;
+	int status, res;
 
-	if (CMD_ARGC < 1)
-	{
-		command_print(CMD_CTX, "pic32mx lock <bank>");
-		return ERROR_OK;
-	}
+	if (CMD_ARGC != 3)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
-	pic32mx_info = bank->driver_priv;
-
-	target = bank->target;
-
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (pic32mx_erase_options(bank) != ERROR_OK)
-	{
-		command_print(CMD_CTX, "pic32mx failed to erase options");
+	if (address < bank->base || address >= (bank->base + bank->size)) {
+		command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
 		return ERROR_OK;
 	}
 
-	/* set readout protection */
-	pic32mx_info->option_bytes.RDP = 0;
-
-	if (pic32mx_write_options(bank) != ERROR_OK)
-	{
-		command_print(CMD_CTX, "pic32mx failed to lock device");
-		return ERROR_OK;
-	}
+	res = ERROR_OK;
+	status = pic32mx_write_word(bank, address, value);
+	if (status & NVMCON_NVMERR)
+		res = ERROR_FLASH_OPERATION_FAILED;
+	if (status & NVMCON_LVDERR)
+		res = ERROR_FLASH_OPERATION_FAILED;
 
-	command_print(CMD_CTX, "pic32mx locked");
+	if (res == ERROR_OK)
+		command_print(CMD_CTX, "pic32mx pgm word complete");
+	else
+		command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
 
 	return ERROR_OK;
 }
 
 COMMAND_HANDLER(pic32mx_handle_unlock_command)
 {
+	uint32_t mchip_cmd;
 	struct target *target = NULL;
-	struct pic32mx_flash_bank *pic32mx_info = NULL;
+	struct mips_m4k_common *mips_m4k;
+	struct mips_ejtag *ejtag_info;
+	int timeout = 10;
 
-	if (CMD_ARGC < 1)
-	{
+	if (CMD_ARGC < 1) {
 		command_print(CMD_CTX, "pic32mx unlock <bank>");
-		return ERROR_OK;
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	struct flash_bank *bank;
@@ -734,189 +847,90 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
 	if (ERROR_OK != retval)
 		return retval;
 
-	pic32mx_info = bank->driver_priv;
-
 	target = bank->target;
+	mips_m4k = target_to_m4k(target);
+	ejtag_info = &mips_m4k->mips32.ejtag_info;
 
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	if (pic32mx_erase_options(bank) != ERROR_OK)
-	{
-		command_print(CMD_CTX, "pic32mx failed to unlock device");
-		return ERROR_OK;
-	}
-
-	if (pic32mx_write_options(bank) != ERROR_OK)
-	{
-		command_print(CMD_CTX, "pic32mx failed to lock device");
-		return ERROR_OK;
-	}
-
-	command_print(CMD_CTX, "pic32mx unlocked");
-
-	return ERROR_OK;
-}
-#endif
-
-#if 0
-static int pic32mx_chip_erase(struct flash_bank *bank)
-{
-	struct target *target = bank->target;
-#if 0
-	uint32_t status;
-#endif
-
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	LOG_INFO("PIC32MX chip erase called");
-
-#if 0
-	/* unlock option flash registers */
-	target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);
-	target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);
-
-	/* chip erase flash memory */
-	target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
-	target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER | FLASH_STRT);
-
-	status = pic32mx_wait_status_busy(bank, 10);
+	/* we have to use the MTAP to perform a full erase */
+	mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+	mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 
-	target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);
-
-	if (status & FLASH_WRPRTERR)
-	{
-		LOG_ERROR("pic32mx device protected");
-		return ERROR_OK;
+	/* first check status of device */
+	mchip_cmd = MCHP_STATUS;
+	mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+	if (mchip_cmd & (1 << 7)) {
+		/* device is not locked */
+		command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
 	}
 
-	if (status & FLASH_PGERR)
-	{
-		LOG_ERROR("pic32mx device programming failed");
-		return ERROR_OK;
-	}
-#endif
-
-	return ERROR_OK;
-}
-#endif
+	/* unlock/erase device */
+	mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
+	jtag_add_sleep(200);
 
-COMMAND_HANDLER(pic32mx_handle_chip_erase_command)
-{
-#if 0
-	int i;
+	mips_ejtag_drscan_8_out(ejtag_info, MCHP_ERASE);
 
-	if (CMD_ARGC != 0)
-	{
-		command_print(CMD_CTX, "pic32mx chip_erase");
-		return ERROR_OK;
-	}
-
-	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (pic32mx_chip_erase(bank) == ERROR_OK)
-	{
-		/* set all sectors as erased */
-		for (i = 0; i < bank->num_sectors; i++)
-		{
-			bank->sectors[i].is_erased = 1;
+	do {
+		mchip_cmd = MCHP_STATUS;
+		mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+		if (timeout-- == 0) {
+			LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+			break;
 		}
+		alive_sleep(1);
+	} while ((mchip_cmd & (1 << 2)) || (!(mchip_cmd & (1 << 3))));
 
-		command_print(CMD_CTX, "pic32mx chip erase complete");
-	}
-	else
-	{
-		command_print(CMD_CTX, "pic32mx chip erase failed");
-	}
-#endif
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
-{
-	uint32_t address, value;
-	int status, res;
-
-	if (CMD_ARGC != 3)
-	{
-		command_print(CMD_CTX, "pic32mx pgm_word <addr> <value> <bank>");
-		return ERROR_OK;
-	}
+	mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+	/* select ejtag tap */
+	mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 
-	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (address < bank->base || address >= (bank->base + bank->size))
-	{
-		command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	res = ERROR_OK;
-	status = pic32mx_write_word(bank, address, value);
-	if (status & NVMCON_NVMERR)
-		res = ERROR_FLASH_OPERATION_FAILED;
-	if (status & NVMCON_LVDERR)
-		res = ERROR_FLASH_OPERATION_FAILED;
-
-	if (res == ERROR_OK)
-		command_print(CMD_CTX, "pic32mx pgm word complete");
-	else
-		command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
+	command_print(CMD_CTX, "pic32mx unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
 
 	return ERROR_OK;
 }
+
 static const struct command_registration pic32mx_exec_command_handlers[] = {
 	{
-		.name = "chip_erase",
-		.handler = &pic32mx_handle_chip_erase_command,
+		.name = "pgm_word",
+		.usage = "<addr> <value> <bank>",
+		.handler = pic32mx_handle_pgm_word_command,
 		.mode = COMMAND_EXEC,
-		.help = "erase device",
+		.help = "program a word",
 	},
 	{
-		.name = "pgm_word",
-		.handler = &pic32mx_handle_pgm_word_command,
+		.name = "unlock",
+		.handler = pic32mx_handle_unlock_command,
 		.mode = COMMAND_EXEC,
-		.help = "program a word",
+		.usage = "[bank_id]",
+		.help = "Unlock/Erase entire device.",
 	},
 	COMMAND_REGISTRATION_DONE
 };
+
 static const struct command_registration pic32mx_command_handlers[] = {
 	{
 		.name = "pic32mx",
 		.mode = COMMAND_ANY,
 		.help = "pic32mx flash command group",
+		.usage = "",
 		.chain = pic32mx_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };
 
 struct flash_driver pic32mx_flash = {
-		.name = "pic32mx",
-		.commands = pic32mx_command_handlers,
-		.flash_bank_command = &pic32mx_flash_bank_command,
-		.erase = &pic32mx_erase,
-		.protect = &pic32mx_protect,
-		.write = &pic32mx_write,
-		.probe = &pic32mx_probe,
-		.auto_probe = &pic32mx_auto_probe,
-		.erase_check = &default_flash_mem_blank_check,
-		.protect_check = &pic32mx_protect_check,
-		.info = &pic32mx_info,
-	};
+	.name = "pic32mx",
+	.commands = pic32mx_command_handlers,
+	.flash_bank_command = pic32mx_flash_bank_command,
+	.erase = pic32mx_erase,
+	.protect = pic32mx_protect,
+	.write = pic32mx_write,
+	.read = default_flash_read,
+	.probe = pic32mx_probe,
+	.auto_probe = pic32mx_auto_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = pic32mx_protect_check,
+	.info = pic32mx_info,
+};