X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Flpc2000.c;h=53ece42d270c8de18ed455bb958beafc9eda72f4;hp=77beac1ca1630650dea8f05f9943392abfb2c65f;hb=a15c11d7d08566dc7005ed7304c5d3f2c425b981;hpb=fdaa8711aef0fb70d289c7cb733313cf3dce3b02

diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 77beac1ca1..53ece42d27 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -12,6 +12,9 @@
  *   by Nemui Trinomius                                                    *
  *   nemuisan_kawausogasuki@live.jp                                        *
  *                                                                         *
+ *   LPC8N04/HNS31xx support Copyright (C) 2018                            *
+ *   by Jean-Christian de Rivaz jcdr [at] innodelec [dot] ch               *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -38,7 +41,7 @@
 
 /**
  * @file
- * flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x and LPC2xxx devices.
+ * flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x,LPC2xxx and NHS31xx devices.
  *
  * @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
  * rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
@@ -77,6 +80,8 @@
  * lpc800:
  * - 810 | 1 | 2 (tested with LPC810/LPC811/LPC812)
  * - 822 | 4 (tested with LPC824)
+ * - 8N04
+ * - NHS31xx (tested with NHS3100)
  *
  * lpc1100:
  * - 11xx
@@ -111,6 +116,8 @@
  * - 408x
  * - 81x
  * - 82x
+ * - 8N04
+ * - NHS31xx
  */
 
 /* Part IDs for autodetection */
@@ -257,6 +264,11 @@
 #define LPC824_201     0x00008241
 #define LPC824_201_1   0x00008242
 
+#define LPC8N04        0x00008A04
+#define NHS3100        0x4e310020
+#define NHS3152        0x4e315220
+#define NHS3153        0x4e315320 /* Only specified in Rev.1 of the datasheet */
+
 #define IAP_CODE_LEN 0x34
 
 #define LPC11xx_REG_SECTORS	24
@@ -526,6 +538,10 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)
 			case 16 * 1024:
 				bank->num_sectors = 16;
 				break;
+			case 30 * 1024:
+				lpc2000_info->cmd51_max_buffer = 1024;	/* For LPC8N04 and NHS31xx, have 8kB of SRAM */
+				bank->num_sectors = 30;			/* There have only 30kB of writable Flash out of 32kB */
+				break;
 			case 32 * 1024:
 				lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */
 				bank->num_sectors = 32;
@@ -1452,6 +1468,14 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
 			bank->size = 32 * 1024;
 			break;
 
+		case LPC8N04:
+		case NHS3100:
+		case NHS3152:
+		case NHS3153:
+			lpc2000_info->variant = lpc800;
+			bank->size = 30 * 1024;
+			break;
+
 		default:
 			LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id);
 			exit(-1);