X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fkinetis.c;h=e8074e35bbffa9873f788ff11195876047256d1d;hp=43b90f1f0c0c7beb78686ff39dd93f1974c11b15;hb=HEAD;hpb=9db3e9879db3d89984eea80dc6fd9b1c3c269e58
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 43b90f1f0c..e8074e35bb 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -1,3 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2011 by Mathias Kuester *
* kesmtp@freenet.de *
@@ -13,19 +15,6 @@
* *
* Copyright (C) 2015 Tomas Vanek *
* vanekt@fbl.cz *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see . *
***************************************************************************/
#ifdef HAVE_CONFIG_H
@@ -38,6 +27,7 @@
#include
#include
#include
+#include
#include
#include
@@ -90,12 +80,13 @@
#define FLEXRAM 0x14000000
#define MSCM_OCMDR0 0x40001400
+#define MSCM_OCMDR1 0x40001404
#define FMC_PFB01CR 0x4001f004
-#define FTFx_FSTAT 0x40020000
-#define FTFx_FCNFG 0x40020001
-#define FTFx_FCCOB3 0x40020004
-#define FTFx_FPROT3 0x40020010
-#define FTFx_FDPROT 0x40020017
+#define FTFX_FSTAT 0x40020000
+#define FTFX_FCNFG 0x40020001
+#define FTFX_FCCOB3 0x40020004
+#define FTFX_FPROT3 0x40020010
+#define FTFX_FDPROT 0x40020017
#define SIM_BASE 0x40047000
#define SIM_BASE_KL28 0x40074000
#define SIM_COPC 0x40048100
@@ -107,6 +98,8 @@
#define SMC_PMSTAT 0x4007E003
#define SMC32_PMCTRL 0x4007E00C
#define SMC32_PMSTAT 0x4007E014
+#define PMC_REGSC 0x4007D002
+#define MC_PMCTRL 0x4007E003
#define MCM_PLACR 0xF000300C
/* Offsets */
@@ -124,14 +117,14 @@
#define PM_CTRL_RUNM_RUN 0x00
/* Commands */
-#define FTFx_CMD_BLOCKSTAT 0x00
-#define FTFx_CMD_SECTSTAT 0x01
-#define FTFx_CMD_LWORDPROG 0x06
-#define FTFx_CMD_SECTERASE 0x09
-#define FTFx_CMD_SECTWRITE 0x0b
-#define FTFx_CMD_MASSERASE 0x44
-#define FTFx_CMD_PGMPART 0x80
-#define FTFx_CMD_SETFLEXRAM 0x81
+#define FTFX_CMD_BLOCKSTAT 0x00
+#define FTFX_CMD_SECTSTAT 0x01
+#define FTFX_CMD_LWORDPROG 0x06
+#define FTFX_CMD_SECTERASE 0x09
+#define FTFX_CMD_SECTWRITE 0x0b
+#define FTFX_CMD_MASSERASE 0x44
+#define FTFX_CMD_PGMPART 0x80
+#define FTFX_CMD_SETFLEXRAM 0x81
/* The older Kinetis K series uses the following SDID layout :
* Bit 31-16 : 0
@@ -198,6 +191,9 @@
#define KINETIS_K_SDID_K60_M150 0x000001C0
#define KINETIS_K_SDID_K70_M150 0x000001D0
+#define KINETIS_K_REVID_MASK 0x0000F000
+#define KINETIS_K_REVID_SHIFT 12
+
#define KINETIS_SDID_SERIESID_MASK 0x00F00000
#define KINETIS_SDID_SERIESID_K 0x00000000
#define KINETIS_SDID_SERIESID_KL 0x00100000
@@ -232,8 +228,30 @@
/* The field originally named DIEID has new name/meaning on KE1x */
#define KINETIS_SDID_PROJECTID_MASK KINETIS_SDID_DIEID_MASK
-#define KINETIS_SDID_PROJECTID_KE1xF 0x00000080
-#define KINETIS_SDID_PROJECTID_KE1xZ 0x00000100
+#define KINETIS_SDID_PROJECTID_KE1XF 0x00000080
+#define KINETIS_SDID_PROJECTID_KE1XZ 0x00000100
+
+/* The S32K series uses a different, incompatible SDID layout :
+ * Bit 31-28 : GENERATION
+ * Bit 27-24 : SUBSERIES
+ * Bit 23-20 : DERIVATE
+ * Bit 19-16 : RAMSIZE
+ * Bit 15-12 : REVID
+ * Bit 11-8 : PACKAGE
+ * Bit 7-0 : FEATURES
+ */
+
+#define KINETIS_SDID_S32K_SERIES_MASK 0xFF000000 /* GENERATION + SUBSERIES */
+#define KINETIS_SDID_S32K_SERIES_K11X 0x11000000
+#define KINETIS_SDID_S32K_SERIES_K14X 0x14000000
+
+#define KINETIS_SDID_S32K_DERIVATE_MASK 0x00F00000
+#define KINETIS_SDID_S32K_DERIVATE_KXX2 0x00200000
+#define KINETIS_SDID_S32K_DERIVATE_KXX3 0x00300000
+#define KINETIS_SDID_S32K_DERIVATE_KXX4 0x00400000
+#define KINETIS_SDID_S32K_DERIVATE_KXX5 0x00500000
+#define KINETIS_SDID_S32K_DERIVATE_KXX6 0x00600000
+#define KINETIS_SDID_S32K_DERIVATE_KXX8 0x00800000
struct kinetis_flash_bank {
struct kinetis_chip *k_chip;
@@ -280,6 +298,11 @@ struct kinetis_chip {
uint32_t progr_accel_ram;
uint32_t sim_base;
+ enum {
+ CT_KINETIS = 0,
+ CT_S32K,
+ } chip_type;
+
enum {
FS_PROGRAM_SECTOR = 1,
FS_PROGRAM_LONGWORD = 2,
@@ -295,6 +318,7 @@ struct kinetis_chip {
KINETIS_CACHE_K, /* invalidate using FMC->PFB0CR/PFB01CR */
KINETIS_CACHE_L, /* invalidate using MCM->PLACR */
KINETIS_CACHE_MSCM, /* devices like KE1xF, invalidate MSCM->OCMDR0 */
+ KINETIS_CACHE_MSCM2, /* devices like S32K, invalidate MSCM->OCMDR0 and MSCM->OCMDR1 */
} cache_type;
enum {
@@ -308,6 +332,7 @@ struct kinetis_chip {
enum {
KINETIS_SMC,
KINETIS_SMC32,
+ KINETIS_MC,
} sysmodectrlr_type;
char name[40];
@@ -396,21 +421,29 @@ const struct flash_driver kinetis_flash;
static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count);
static int kinetis_probe_chip(struct kinetis_chip *k_chip);
+static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip);
static int kinetis_auto_probe(struct flash_bank *bank);
static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
{
- int retval;
LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
- retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
+ struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
+ if (!ap) {
+ LOG_DEBUG("MDM: failed to get AP");
+ return ERROR_FAIL;
+ }
+
+ int retval = dap_queue_ap_write(ap, reg, value);
if (retval != ERROR_OK) {
LOG_DEBUG("MDM: failed to queue a write request");
+ dap_put_ap(ap);
return retval;
}
retval = dap_run(dap);
+ dap_put_ap(ap);
if (retval != ERROR_OK) {
LOG_DEBUG("MDM: dap_run failed");
return retval;
@@ -422,15 +455,21 @@ static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint3
static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
{
- int retval;
+ struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
+ if (!ap) {
+ LOG_DEBUG("MDM: failed to get AP");
+ return ERROR_FAIL;
+ }
- retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
+ int retval = dap_queue_ap_read(ap, reg, result);
if (retval != ERROR_OK) {
LOG_DEBUG("MDM: failed to queue a read request");
+ dap_put_ap(ap);
return retval;
}
retval = dap_run(dap);
+ dap_put_ap(ap);
if (retval != ERROR_OK) {
LOG_DEBUG("MDM: dap_run failed");
return retval;
@@ -786,12 +825,18 @@ COMMAND_HANDLER(kinetis_check_flash_security_status)
if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
uint32_t stats[32];
+ struct adiv5_ap *ap = dap_get_ap(dap, MDM_AP);
+ if (!ap) {
+ LOG_ERROR("MDM: failed to get AP");
+ return ERROR_OK;
+ }
for (unsigned int i = 0; i < 32; i++) {
stats[i] = MDM_STAT_FREADY;
- dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
+ dap_queue_ap_read(ap, MDM_REG_STAT, &stats[i]);
}
retval = dap_run(dap);
+ dap_put_ap(ap);
if (retval != ERROR_OK) {
LOG_DEBUG("MDM: dap_run failed when validating secured state");
return ERROR_OK;
@@ -862,6 +907,8 @@ static int kinetis_chip_options(struct kinetis_chip *k_chip, int argc, const cha
if (strcmp(argv[i], "-sim-base") == 0) {
if (i + 1 < argc)
k_chip->sim_base = strtoul(argv[++i], NULL, 0);
+ } else if (strcmp(argv[i], "-s32k") == 0) {
+ k_chip->chip_type = CT_S32K;
} else
LOG_ERROR("Unsupported flash bank option %s", argv[i]);
}
@@ -882,9 +929,9 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
k_chip = kinetis_get_chip(target);
- if (k_chip == NULL) {
+ if (!k_chip) {
k_chip = calloc(sizeof(struct kinetis_chip), 1);
- if (k_chip == NULL) {
+ if (!k_chip) {
LOG_ERROR("No memory");
return ERROR_FAIL;
}
@@ -915,11 +962,11 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
static void kinetis_free_driver_priv(struct flash_bank *bank)
{
struct kinetis_flash_bank *k_bank = bank->driver_priv;
- if (k_bank == NULL)
+ if (!k_bank)
return;
struct kinetis_chip *k_chip = k_bank->k_chip;
- if (k_chip == NULL)
+ if (!k_chip)
return;
k_chip->num_banks--;
@@ -933,7 +980,7 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
unsigned num_blocks;
struct kinetis_flash_bank *k_bank;
struct flash_bank *bank;
- char base_name[69], name[80], num[4];
+ char base_name[69], name[87], num[11];
char *class, *p;
num_blocks = k_chip->num_pflash_blocks + k_chip->num_nvm_blocks;
@@ -985,7 +1032,7 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
}
bank = calloc(sizeof(struct flash_bank), 1);
- if (bank == NULL)
+ if (!bank)
return ERROR_FAIL;
bank->target = k_chip->target;
@@ -1125,7 +1172,13 @@ static int kinetis_disable_wdog(struct kinetis_chip *k_chip)
int retval;
if (!k_chip->probed) {
- retval = kinetis_probe_chip(k_chip);
+ switch (k_chip->chip_type) {
+ case CT_S32K:
+ retval = kinetis_probe_chip_s32k(k_chip);
+ break;
+ default:
+ retval = kinetis_probe_chip(k_chip);
+ }
if (retval != ERROR_OK)
return retval;
}
@@ -1174,7 +1227,7 @@ COMMAND_HANDLER(kinetis_disable_wdog_handler)
struct target *target = get_current_target(CMD_CTX);
struct kinetis_chip *k_chip = kinetis_get_chip(target);
- if (k_chip == NULL)
+ if (!k_chip)
return ERROR_FAIL;
if (CMD_ARGC > 0)
@@ -1209,7 +1262,7 @@ static int kinetis_ftfx_decode_error(uint8_t fstat)
static int kinetis_ftfx_clear_error(struct target *target)
{
/* reset error flags */
- return target_write_u8(target, FTFx_FSTAT, 0x70);
+ return target_write_u8(target, FTFX_FSTAT, 0x70);
}
@@ -1220,7 +1273,7 @@ static int kinetis_ftfx_prepare(struct target *target)
/* wait until busy */
for (unsigned int i = 0; i < 50; i++) {
- result = target_read_u8(target, FTFx_FSTAT, &fstat);
+ result = target_read_u8(target, FTFX_FSTAT, &fstat);
if (result != ERROR_OK)
return result;
@@ -1300,7 +1353,7 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(reg_params[1].value, 0, 32, wcount);
buf_set_u32(reg_params[2].value, 0, 32, source->address);
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
- buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
+ buf_set_u32(reg_params[4].value, 0, 32, FTFX_FSTAT);
retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
0, NULL,
@@ -1314,12 +1367,12 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
- retval = target_read_u8(target, FTFx_FSTAT, &fstat);
+ retval = target_read_u8(target, FTFX_FSTAT, &fstat);
if (retval == ERROR_OK) {
retval = kinetis_ftfx_decode_error(fstat);
/* reset error flags */
- target_write_u8(target, FTFx_FSTAT, 0x70);
+ target_write_u8(target, FTFX_FSTAT, 0x70);
}
} else if (retval != ERROR_OK)
LOG_ERROR("Error executing kinetis Flash programming algorithm");
@@ -1369,7 +1422,7 @@ static int kinetis_protect_check(struct flash_bank *bank)
if (k_bank->flash_class == FC_PFLASH) {
/* read protection register */
- result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
+ result = target_read_u32(bank->target, FTFX_FPROT3, &fprot);
if (result != ERROR_OK)
return result;
@@ -1379,7 +1432,7 @@ static int kinetis_protect_check(struct flash_bank *bank)
uint8_t fdprot;
/* read protection register */
- result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
+ result = target_read_u8(bank->target, FTFX_FDPROT, &fdprot);
if (result != ERROR_OK)
return result;
@@ -1428,7 +1481,7 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
k_bank = &(k_chip->banks[bank_idx]);
bank_iter = k_bank->bank;
- if (bank_iter == NULL) {
+ if (!bank_iter) {
LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
continue;
}
@@ -1475,18 +1528,18 @@ static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t fa
uint8_t fstat;
int64_t ms_timeout = timeval_ms() + 250;
- result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
+ result = target_write_memory(target, FTFX_FCCOB3, 4, 3, command);
if (result != ERROR_OK)
return result;
/* start command */
- result = target_write_u8(target, FTFx_FSTAT, 0x80);
+ result = target_write_u8(target, FTFX_FSTAT, 0x80);
if (result != ERROR_OK)
return result;
/* wait for done */
do {
- result = target_read_u8(target, FTFx_FSTAT, &fstat);
+ result = target_read_u8(target, FTFX_FSTAT, &fstat);
if (result != ERROR_OK)
return result;
@@ -1528,6 +1581,17 @@ static int kinetis_read_pmstat(struct kinetis_chip *k_chip, uint8_t *pmstat)
if (result == ERROR_OK)
*pmstat = stat32 & 0xff;
return result;
+
+ case KINETIS_MC:
+ /* emulate SMC by reading PMC_REGSC bit 3 (VLPRS) */
+ result = target_read_u8(target, PMC_REGSC, pmstat);
+ if (result == ERROR_OK) {
+ if (*pmstat & 0x08)
+ *pmstat = PM_STAT_VLPR;
+ else
+ *pmstat = PM_STAT_RUN;
+ }
+ return result;
}
return ERROR_FAIL;
}
@@ -1538,7 +1602,7 @@ static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
uint8_t pmstat;
struct target *target;
- if (k_chip == NULL) {
+ if (!k_chip) {
LOG_ERROR("Chip not probed.");
return ERROR_FAIL;
}
@@ -1568,6 +1632,10 @@ static int kinetis_check_run_mode(struct kinetis_chip *k_chip)
case KINETIS_SMC32:
result = target_write_u32(target, SMC32_PMCTRL, PM_CTRL_RUNM_RUN);
break;
+
+ case KINETIS_MC:
+ result = target_write_u32(target, MC_PMCTRL, PM_CTRL_RUNM_RUN);
+ break;
}
if (result != ERROR_OK)
return result;
@@ -1609,6 +1677,12 @@ static void kinetis_invalidate_flash_cache(struct kinetis_chip *k_chip)
/* disable data prefetch and flash speculate */
break;
+ case KINETIS_CACHE_MSCM2:
+ target_write_u32(target, MSCM_OCMDR0, 0x30);
+ target_write_u32(target, MSCM_OCMDR1, 0x30);
+ /* disable data prefetch and flash speculate */
+ break;
+
default:
break;
}
@@ -1641,7 +1715,7 @@ static int kinetis_erase(struct flash_bank *bank, unsigned int first,
*/
for (unsigned int i = first; i <= last; i++) {
/* set command and sector address */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTERASE, k_bank->prog_base + bank->sectors[i].offset,
0, 0, 0, 0, 0, 0, 0, 0, NULL);
if (result != ERROR_OK) {
@@ -1679,7 +1753,7 @@ static int kinetis_make_ram_ready(struct target *target)
uint8_t ftfx_fcnfg;
/* check if ram ready */
- result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;
@@ -1687,13 +1761,13 @@ static int kinetis_make_ram_ready(struct target *target)
return ERROR_OK; /* ram ready */
/* make flex ram available */
- result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
+ result = kinetis_ftfx_command(target, FTFX_CMD_SETFLEXRAM, 0x00ff0000,
0, 0, 0, 0, 0, 0, 0, 0, NULL);
if (result != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
/* check again */
- result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
+ result = target_read_u8(target, FTFX_FCNFG, &ftfx_fcnfg);
if (result != ERROR_OK)
return result;
@@ -1766,7 +1840,7 @@ static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer
}
/* execute section-write command */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTWRITE,
k_bank->prog_base + offset - align_begin,
chunk_count>>8, chunk_count, 0, 0,
0, 0, 0, 0, &ftfx_fstat);
@@ -1840,7 +1914,7 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
uint32_t old_count = count;
count = (old_count | 3) + 1;
new_buffer = malloc(count);
- if (new_buffer == NULL) {
+ if (!new_buffer) {
LOG_ERROR("odd number of bytes to write and no memory "
"for padding buffer");
return ERROR_FAIL;
@@ -1869,7 +1943,7 @@ static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, k_bank->prog_base + offset,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_LWORDPROG, k_bank->prog_base + offset,
buffer[3], buffer[2], buffer[1], buffer[0],
0, 0, 0, 0, &ftfx_fstat);
@@ -2018,6 +2092,174 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
}
+static int kinetis_probe_chip_s32k(struct kinetis_chip *k_chip)
+{
+ int result;
+ uint8_t fcfg1_eesize, fcfg1_depart;
+ uint32_t ee_size = 0;
+ uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
+ unsigned int generation = 0, subseries = 0, derivate = 0;
+
+ struct target *target = k_chip->target;
+ k_chip->probed = false;
+ k_chip->pflash_sector_size = 0;
+ k_chip->pflash_base = 0;
+ k_chip->nvm_base = 0x10000000;
+ k_chip->progr_accel_ram = FLEXRAM;
+ k_chip->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR;
+ k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
+
+ if (k_chip->sim_base == 0)
+ k_chip->sim_base = SIM_BASE;
+
+ result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ if (result != ERROR_OK)
+ return result;
+
+ generation = (k_chip->sim_sdid) >> 28 & 0x0f;
+ subseries = (k_chip->sim_sdid) >> 24 & 0x0f;
+ derivate = (k_chip->sim_sdid) >> 20 & 0x0f;
+
+ switch (k_chip->sim_sdid & KINETIS_SDID_S32K_SERIES_MASK) {
+ case KINETIS_SDID_S32K_SERIES_K11X:
+ k_chip->cache_type = KINETIS_CACHE_L;
+ k_chip->num_pflash_blocks = 1;
+ k_chip->num_nvm_blocks = 1;
+ /* Non-interleaved */
+ k_chip->max_flash_prog_size = 512;
+
+ switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) {
+ case KINETIS_SDID_S32K_DERIVATE_KXX6:
+ /* S32K116 CPU 48Mhz Flash 128KB RAM 17KB+2KB */
+ /* Non-Interleaved */
+ k_chip->pflash_size = 128 << 10;
+ k_chip->pflash_sector_size = 2 << 10;
+ /* Non-Interleaved */
+ k_chip->nvm_size = 32 << 10;
+ k_chip->nvm_sector_size = 2 << 10;
+ break;
+ case KINETIS_SDID_S32K_DERIVATE_KXX8:
+ /* S32K118 CPU 80Mhz Flash 256KB+32KB RAM 32KB+4KB */
+ /* Non-Interleaved */
+ k_chip->pflash_size = 256 << 10;
+ k_chip->pflash_sector_size = 2 << 10;
+ /* Non-Interleaved */
+ k_chip->nvm_size = 32 << 10;
+ k_chip->nvm_sector_size = 2 << 10;
+ break;
+ }
+ break;
+
+ case KINETIS_SDID_S32K_SERIES_K14X:
+ k_chip->cache_type = KINETIS_CACHE_MSCM2;
+ k_chip->num_pflash_blocks = 1;
+ k_chip->num_nvm_blocks = 1;
+ /* Non-interleaved */
+ k_chip->max_flash_prog_size = 512;
+ switch (k_chip->sim_sdid & KINETIS_SDID_S32K_DERIVATE_MASK) {
+ case KINETIS_SDID_S32K_DERIVATE_KXX2:
+ case KINETIS_SDID_S32K_DERIVATE_KXX3:
+ /* S32K142/S32K142W CPU 80Mhz Flash 256KB+64KB RAM 32KB+4KB */
+ /* Non-Interleaved */
+ k_chip->pflash_size = 256 << 10;
+ k_chip->pflash_sector_size = 2 << 10;
+ /* Non-Interleaved */
+ k_chip->nvm_size = 64 << 10;
+ k_chip->nvm_sector_size = 2 << 10;
+ break;
+ case KINETIS_SDID_S32K_DERIVATE_KXX4:
+ case KINETIS_SDID_S32K_DERIVATE_KXX5:
+ /* S32K144/S32K144W CPU 80Mhz Flash 512KB+64KB RAM 64KB+4KB */
+ /* Interleaved */
+ k_chip->pflash_size = 512 << 10;
+ k_chip->pflash_sector_size = 4 << 10;
+ /* Non-Interleaved */
+ k_chip->nvm_size = 64 << 10;
+ k_chip->nvm_sector_size = 2 << 10;
+ break;
+ case KINETIS_SDID_S32K_DERIVATE_KXX6:
+ /* S32K146 CPU 80Mhz Flash 1024KB+64KB RAM 128KB+4KB */
+ /* Interleaved */
+ k_chip->pflash_size = 1024 << 10;
+ k_chip->pflash_sector_size = 4 << 10;
+ k_chip->num_pflash_blocks = 2;
+ /* Non-Interleaved */
+ k_chip->nvm_size = 64 << 10;
+ k_chip->nvm_sector_size = 2 << 10;
+ break;
+ case KINETIS_SDID_S32K_DERIVATE_KXX8:
+ /* S32K148 CPU 80Mhz Flash 1536KB+512KB RAM 256KB+4KB */
+ /* Interleaved */
+ k_chip->pflash_size = 1536 << 10;
+ k_chip->pflash_sector_size = 4 << 10;
+ k_chip->num_pflash_blocks = 3;
+ /* Interleaved */
+ k_chip->nvm_size = 512 << 10;
+ k_chip->nvm_sector_size = 4 << 10;
+ /* Interleaved */
+ k_chip->max_flash_prog_size = 1 << 10;
+ break;
+ }
+ break;
+
+ default:
+ LOG_ERROR("Unsupported S32K1xx-series");
+ }
+
+ if (k_chip->pflash_sector_size == 0) {
+ LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, k_chip->sim_sdid);
+ return ERROR_FLASH_OPER_UNSUPPORTED;
+ }
+
+ result = target_read_u32(target, k_chip->sim_base + SIM_FCFG1_OFFSET, &k_chip->sim_fcfg1);
+ if (result != ERROR_OK)
+ return result;
+ k_chip->sim_fcfg2 = 0; /* S32K1xx does not implement FCFG2 register. */
+
+ fcfg1_depart = (k_chip->sim_fcfg1 >> 12) & 0x0f;
+ fcfg1_eesize = (k_chip->sim_fcfg1 >> 16) & 0x0f;
+ if (fcfg1_eesize <= 9)
+ ee_size = (16 << (10 - fcfg1_eesize));
+ if ((fcfg1_depart & 0x8) == 0) {
+ /* Binary 0xxx values encode the amount reserved for EEPROM emulation. */
+ if (fcfg1_depart)
+ k_chip->dflash_size = k_chip->nvm_size - (4096 << fcfg1_depart);
+ else
+ k_chip->dflash_size = k_chip->nvm_size;
+ } else {
+ /* Binary 1xxx valued encode the DFlash size. */
+ if (fcfg1_depart & 0x7)
+ k_chip->dflash_size = 4096 << (fcfg1_depart & 0x7);
+ else
+ k_chip->dflash_size = 0;
+ }
+
+ snprintf(k_chip->name, sizeof(k_chip->name), "S32K%u%u%u",
+ generation, subseries, derivate);
+
+ pflash_size_k = k_chip->pflash_size / 1024;
+ dflash_size_k = k_chip->dflash_size / 1024;
+
+ LOG_INFO("%s detected: %u flash blocks", k_chip->name, k_chip->num_pflash_blocks + k_chip->num_nvm_blocks);
+ LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k);
+
+ nvm_size_k = k_chip->nvm_size / 1024;
+
+ if (k_chip->num_nvm_blocks) {
+ LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %"
+ PRIu32 " bytes FlexRAM",
+ k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
+ }
+
+ k_chip->probed = true;
+
+ if (create_banks)
+ kinetis_create_missing_banks(k_chip);
+
+ return ERROR_OK;
+}
+
+
static int kinetis_probe_chip(struct kinetis_chip *k_chip)
{
int result;
@@ -2134,6 +2376,24 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
}
}
+ /* first revision of some devices has no SMC */
+ switch (mcu_type) {
+ case KINETIS_K_SDID_K10_M100:
+ case KINETIS_K_SDID_K20_M100:
+ case KINETIS_K_SDID_K30_M100:
+ case KINETIS_K_SDID_K40_M100:
+ case KINETIS_K_SDID_K60_M100:
+ {
+ uint32_t revid = (k_chip->sim_sdid & KINETIS_K_REVID_MASK) >> KINETIS_K_REVID_SHIFT;
+ /* highest bit set corresponds to rev 2.x */
+ if (revid <= 7) {
+ k_chip->sysmodectrlr_type = KINETIS_MC;
+ strcat(name, " Rev 1.x");
+ }
+ }
+ break;
+ }
+
} else {
/* Newer K-series or KL series MCU */
familyid = (k_chip->sim_sdid & KINETIS_SDID_FAMILYID_MASK) >> KINETIS_SDID_FAMILYID_SHIFT;
@@ -2405,8 +2665,8 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
k_chip->watchdog_type = KINETIS_WDOG32_KE1X;
switch (k_chip->sim_sdid &
(KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK | KINETIS_SDID_PROJECTID_MASK)) {
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xZ:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1xZ:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XZ:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX5 | KINETIS_SDID_PROJECTID_KE1XZ:
/* KE1xZ: FTFE, 2kB sectors */
k_chip->pflash_sector_size = 2<<10;
k_chip->nvm_sector_size = 2<<10;
@@ -2420,9 +2680,9 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
familyid, subfamid, cpu_mhz / 10);
break;
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1xF:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1xF:
- case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1xF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX4 | KINETIS_SDID_PROJECTID_KE1XF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX6 | KINETIS_SDID_PROJECTID_KE1XF:
+ case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX8 | KINETIS_SDID_PROJECTID_KE1XF:
/* KE1xF: FTFE, 4kB sectors */
k_chip->pflash_sector_size = 4<<10;
k_chip->nvm_sector_size = 2<<10;
@@ -2578,7 +2838,7 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
else
k_chip->pflash_size = k_chip->fcfg2_maxaddr0_shifted * num_blocks / 2;
if (k_chip->pflash_size != 2048<<10)
- LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", k_chip->pflash_size>>10);
+ LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %" PRIu32 " KB", k_chip->pflash_size>>10);
break;
default:
@@ -2614,12 +2874,12 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
snprintf(k_chip->name, sizeof(k_chip->name), name, flash_marking);
LOG_INFO("Kinetis %s detected: %u flash blocks", k_chip->name, num_blocks);
- LOG_INFO("%u PFlash banks: %" PRIu32 "k total", k_chip->num_pflash_blocks, pflash_size_k);
+ LOG_INFO("%u PFlash banks: %" PRIu32 " KiB total", k_chip->num_pflash_blocks, pflash_size_k);
if (k_chip->num_nvm_blocks) {
nvm_size_k = k_chip->nvm_size / 1024;
dflash_size_k = k_chip->dflash_size / 1024;
- LOG_INFO("%u FlexNVM banks: %" PRIu32 "k total, %" PRIu32 "k available as data flash, %" PRIu32 "bytes FlexRAM",
- k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
+ LOG_INFO("%u FlexNVM banks: %" PRIu32 " KiB total, %" PRIu32 " KiB available as data flash, %"
+ PRIu32 " bytes FlexRAM", k_chip->num_nvm_blocks, nvm_size_k, dflash_size_k, ee_size);
}
k_chip->probed = true;
@@ -2645,7 +2905,13 @@ static int kinetis_probe(struct flash_bank *bank)
k_bank->probed = false;
if (!k_chip->probed) {
- result = kinetis_probe_chip(k_chip);
+ switch (k_chip->chip_type) {
+ case CT_S32K:
+ result = kinetis_probe_chip_s32k(k_chip);
+ break;
+ default:
+ result = kinetis_probe_chip(k_chip);
+ }
if (result != ERROR_OK)
return result;
}
@@ -2668,7 +2934,7 @@ static int kinetis_probe(struct flash_bank *bank)
k_bank->protection_block = bank->num_prot_blocks * k_bank->bank_number;
size_k = bank->size / 1024;
- LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %u",
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k PFlash, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
} else if (k_bank->bank_number < num_blocks) {
@@ -2708,7 +2974,7 @@ static int kinetis_probe(struct flash_bank *bank)
}
size_k = bank->size / 1024;
- LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %u",
+ LOG_DEBUG("Kinetis bank %u: %" PRIu32 "k FlexNVM, FTFx base 0x%08" PRIx32 ", sect %" PRIu32,
k_bank->bank_number, size_k, k_bank->prog_base, k_bank->sector_size);
} else {
@@ -2717,33 +2983,33 @@ static int kinetis_probe(struct flash_bank *bank)
return ERROR_FLASH_BANK_INVALID;
}
- fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
- fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
- fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
+ /* S32K1xx does not implement FCFG2 register. Skip checks. */
+ if (k_chip->chip_type != CT_S32K) {
+ fcfg2_pflsh = (uint8_t)((k_chip->sim_fcfg2 >> 23) & 0x01);
+ fcfg2_maxaddr0 = (uint8_t)((k_chip->sim_fcfg2 >> 24) & 0x7f);
+ fcfg2_maxaddr1 = (uint8_t)((k_chip->sim_fcfg2 >> 16) & 0x7f);
- if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
- LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
- " please report to OpenOCD mailing list", fcfg2_maxaddr0);
+ if (k_bank->bank_number == 0 && k_chip->fcfg2_maxaddr0_shifted != bank->size)
+ LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr0);
- if (fcfg2_pflsh) {
- if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
- LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
- " please report to OpenOCD mailing list", fcfg2_maxaddr1);
- } else {
- if (k_bank->bank_number == first_nvm_bank
- && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
- LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
- " please report to OpenOCD mailing list", fcfg2_maxaddr1);
+ if (fcfg2_pflsh) {
+ if (k_bank->bank_number == 1 && k_chip->fcfg2_maxaddr1_shifted != bank->size)
+ LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr1);
+ } else {
+ if (k_bank->bank_number == first_nvm_bank
+ && k_chip->fcfg2_maxaddr1_shifted != k_chip->dflash_size)
+ LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
+ " please report to OpenOCD mailing list", fcfg2_maxaddr1);
+ }
}
- if (bank->sectors) {
- free(bank->sectors);
- bank->sectors = NULL;
- }
- if (bank->prot_blocks) {
- free(bank->prot_blocks);
- bank->prot_blocks = NULL;
- }
+ free(bank->sectors);
+ bank->sectors = NULL;
+
+ free(bank->prot_blocks);
+ bank->prot_blocks = NULL;
if (k_bank->sector_size == 0) {
LOG_ERROR("Unknown sector size for bank %u", bank->bank_number);
@@ -2781,7 +3047,7 @@ static int kinetis_auto_probe(struct flash_bank *bank)
return kinetis_probe(bank);
}
-static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
+static int kinetis_info(struct flash_bank *bank, struct command_invocation *cmd)
{
const char *bank_class_names[] = {
"(ANY)", "PFlash", "FlexNVM", "FlexRAM"
@@ -2791,7 +3057,7 @@ static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
struct kinetis_chip *k_chip = k_bank->k_chip;
uint32_t size_k = bank->size / 1024;
- snprintf(buf, buf_size,
+ command_print_sameline(cmd,
"%s %s: %" PRIu32 "k %s bank %s at " TARGET_ADDR_FMT,
bank->driver->name, k_chip->name,
size_k, bank_class_names[k_bank->flash_class],
@@ -2806,7 +3072,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
struct kinetis_chip *k_chip = k_bank->k_chip;
int result;
- /* suprisingly blank check does not work in VLPR and HSRUN modes */
+ /* surprisingly blank check does not work in VLPR and HSRUN modes */
result = kinetis_check_run_mode(k_chip);
if (result != ERROR_OK)
return result;
@@ -2830,7 +3096,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
if (use_block_cmd) {
/* check if whole bank is blank */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, k_bank->prog_base,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_BLOCKSTAT, k_bank->prog_base,
0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
if (result != ERROR_OK)
@@ -2843,7 +3109,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
/* the whole bank is not erased, check sector-by-sector */
for (unsigned int i = 0; i < bank->num_sectors; i++) {
/* normal margin */
- result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
+ result = kinetis_ftfx_command(bank->target, FTFX_CMD_SECTSTAT,
k_bank->prog_base + bank->sectors[i].offset,
1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
@@ -2887,19 +3153,24 @@ COMMAND_HANDLER(kinetis_nvm_partition)
k_chip = kinetis_get_chip(target);
+ if (k_chip->chip_type == CT_S32K) {
+ LOG_ERROR("NVM partition not supported on S32K1xx (yet).");
+ return ERROR_FAIL;
+ }
+
if (CMD_ARGC >= 2) {
if (strcmp(CMD_ARGV[0], "dataflash") == 0)
sz_type = DF_SIZE;
else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
sz_type = EEBKP_SIZE;
- par = strtoul(CMD_ARGV[1], NULL, 10);
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], par);
while (par >> (log2 + 3))
log2++;
}
switch (sz_type) {
case SHOW_INFO:
- if (k_chip == NULL) {
+ if (!k_chip) {
LOG_ERROR("Chip not probed.");
return ERROR_FAIL;
}
@@ -2948,11 +3219,13 @@ COMMAND_HANDLER(kinetis_nvm_partition)
break;
}
- if (CMD_ARGC == 3)
- ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
- else if (CMD_ARGC >= 4) {
- ee1 = strtoul(CMD_ARGV[2], NULL, 10);
- ee2 = strtoul(CMD_ARGV[3], NULL, 10);
+ if (CMD_ARGC == 3) {
+ unsigned long eex;
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], eex);
+ ee1 = ee2 = eex / 2;
+ } else if (CMD_ARGC >= 4) {
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], ee1);
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ee2);
}
enable = ee1 + ee2 > 0;
@@ -2995,7 +3268,7 @@ COMMAND_HANDLER(kinetis_nvm_partition)
if (result != ERROR_OK)
return result;
- result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
+ result = kinetis_ftfx_command(target, FTFX_CMD_PGMPART, load_flex_ram,
ee_size_code, flex_nvm_partition_code, 0, 0,
0, 0, 0, 0, NULL);
if (result != ERROR_OK)
@@ -3047,7 +3320,7 @@ COMMAND_HANDLER(kinetis_fopt_handler)
return ERROR_COMMAND_SYNTAX_ERROR;
if (CMD_ARGC == 1) {
- fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
+ COMMAND_PARSE_NUMBER(u8, CMD_ARGV[0], fcf_fopt);
} else {
command_print(CMD, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
}