X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91sam4l.c;h=74d5dbc6812a93dc0cd8a7f2eef5b4b457159e84;hp=bb84185205b5834ae91745911f138e46fe629b33;hb=f3b1405fddf0b32af27ad3894841f7d1702d8e5a;hpb=9cabe333e14435ed9c92bfcf31b1685634ca1acf;ds=sidebyside diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c index bb84185205..74d5dbc681 100644 --- a/src/flash/nor/at91sam4l.c +++ b/src/flash/nor/at91sam4l.c @@ -24,18 +24,20 @@ #include "imp.h" +#include + /* At this time, the SAM4L Flash is available in these capacities: * ATSAM4Lx4xx: 256KB (512 pages) * ATSAM4Lx2xx: 128KB (256 pages) * ATSAM4Lx8xx: 512KB (1024 pages) */ -/* There are 16 lockable regions regardless of overall capacity. The number +/* There are 16 lockable regions regardless of overall capacity. The number * of pages per sector is therefore dependant on capacity. */ #define SAM4L_NUM_SECTORS 16 /* Locations in memory map */ -#define SAM4L_FLASH 0x00000000 /* Flash region */ +#define SAM4L_FLASH ((uint32_t)0x00000000) /* Flash region */ #define SAM4L_FLASH_USER 0x00800000 /* Flash user page region */ #define SAM4L_FLASHCALW 0x400A0000 /* Flash controller */ #define SAM4L_CHIPID 0x400E0740 /* Chip Identification */ @@ -75,6 +77,14 @@ #define SAM4L_FMCD_CMDKEY 0xA5UL /* 'key' to issue commands, see 14.10.2 */ + +/* SMAP registers and bits */ +#define SMAP_BASE 0x400A3000 + +#define SMAP_SCR (SMAP_BASE + 8) +#define SMAP_SCR_HCR (1 << 1) + + struct sam4l_chip_info { uint32_t id; uint32_t exid; @@ -82,7 +92,7 @@ struct sam4l_chip_info { }; /* These are taken from Table 9-1 in 42023E-SAM-07/2013 */ -static struct sam4l_chip_info sam4l_known_chips[] = { +static const struct sam4l_chip_info sam4l_known_chips[] = { { 0xAB0B0AE0, 0x1400000F, "ATSAM4LC8C" }, { 0xAB0A09E0, 0x0400000F, "ATSAM4LC4C" }, { 0xAB0A07E0, 0x0400000F, "ATSAM4LC2C" }, @@ -104,13 +114,13 @@ static struct sam4l_chip_info sam4l_known_chips[] = { }; /* Meaning of SRAMSIZ field in CHIPID, see 9.3.1 in 42023E-SAM-07/2013 */ -static uint16_t sam4l_ram_sizes[16] = { 48, 1, 2, 6, 24, 4, 80, 160, 8, 16, 32, 64, 128, 256, 96, 512 }; +static const uint16_t sam4l_ram_sizes[16] = { 48, 1, 2, 6, 24, 4, 80, 160, 8, 16, 32, 64, 128, 256, 96, 512 }; /* Meaning of PSZ field in FPR, see 14.10.4 in 42023E-SAM-07/2013 */ static const uint16_t sam4l_page_sizes[8] = { 32, 64, 128, 256, 512, 1024, 2048, 4096 }; struct sam4l_info { - struct sam4l_chip_info *details; + const struct sam4l_chip_info *details; uint32_t flash_kb; uint32_t ram_kb; @@ -230,7 +240,7 @@ FLASH_BANK_COMMAND_HANDLER(sam4l_flash_bank_command) return ERROR_OK; } -static struct sam4l_chip_info *sam4l_find_chip_name(uint32_t id, uint32_t exid) +static const struct sam4l_chip_info *sam4l_find_chip_name(uint32_t id, uint32_t exid) { unsigned int i; @@ -253,7 +263,7 @@ static int sam4l_check_page_erased(struct flash_bank *bank, uint32_t pn, /* Issue a quick page read to verify that we've erased this page */ res = sam4l_flash_command(bank->target, SAM4L_FCMD_QPR, pn); if (res != ERROR_OK) { - LOG_ERROR("Quick page read %d failed", pn); + LOG_ERROR("Quick page read %" PRIu32 " failed", pn); return res; } @@ -307,7 +317,7 @@ static int sam4l_probe(struct flash_bank *bank) chip->flash_kb = 512; break; default: - LOG_ERROR("Unknown flash size (chip ID is %08X), assuming 128K", id); + LOG_ERROR("Unknown flash size (chip ID is %08" PRIx32 "), assuming 128K", id); chip->flash_kb = 128; break; } @@ -351,8 +361,8 @@ static int sam4l_probe(struct flash_bank *bank) /* Done */ chip->probed = true; - LOG_INFO("SAM4L MCU: %s (Rev %c) (%uKB Flash with %d %dB pages, %uKB RAM)", - chip->details ? chip->details->name : "unknown", 'A' + (id & 0xF), + LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRId32 "B pages, %" PRIu32 "KB RAM)", + chip->details ? chip->details->name : "unknown", (char)('A' + (id & 0xF)), chip->flash_kb, chip->num_pages, chip->page_size, chip->ram_kb); return ERROR_OK; @@ -495,10 +505,12 @@ static int sam4l_erase(struct flash_bank *bank, int first, int last) /* Write an entire page from host buffer 'buf' to page-aligned 'address' in the * Flash. */ static int sam4l_write_page(struct sam4l_info *chip, struct target *target, - uint32_t address, uint8_t *buf) + uint32_t address, const uint8_t *buf) { int res; + LOG_DEBUG("sam4l_write_page address=%08" PRIx32, address); + /* Clear the page buffer before we write to it */ res = sam4l_flash_command(target, SAM4L_FCMD_CPB, -1); if (res != ERROR_OK) { @@ -527,7 +539,7 @@ static int sam4l_write_page(struct sam4l_info *chip, struct target *target, /* Write partial contents into page-aligned 'address' on the Flash from host * buffer 'buf' by writing 'nb' of 'buf' at 'offset' into the Flash page. */ static int sam4l_write_page_partial(struct sam4l_info *chip, - struct flash_bank *bank, uint32_t address, uint8_t *buf, + struct flash_bank *bank, uint32_t address, const uint8_t *buf, uint32_t page_offset, uint32_t nb) { int res; @@ -535,6 +547,8 @@ static int sam4l_write_page_partial(struct sam4l_info *chip, if (!pg) return ERROR_FAIL; + LOG_DEBUG("sam4l_write_page_partial address=%08" PRIx32 " nb=%08" PRIx32, address, nb); + assert(page_offset + nb < chip->page_size); assert((address % chip->page_size) == 0); @@ -556,13 +570,15 @@ static int sam4l_write_page_partial(struct sam4l_info *chip, return res; } -static int sam4l_write(struct flash_bank *bank, uint8_t *buffer, +static int sam4l_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count) { int res; uint32_t nb = 0; struct sam4l_info *chip = (struct sam4l_info *)bank->driver_priv; + LOG_DEBUG("sam4l_write offset=%08" PRIx32 " count=%08" PRIx32, offset, count); + if (bank->target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); @@ -605,14 +621,14 @@ static int sam4l_write(struct flash_bank *bank, uint8_t *buffer, for (int i = 0; i < np; i++) { if (count >= chip->page_size) { res = sam4l_write_page(chip, bank->target, - bank->base + (i * chip->page_size), + bank->base + offset, buffer + (i * chip->page_size)); /* Advance one page */ offset += chip->page_size; count -= chip->page_size; } else { res = sam4l_write_page_partial(chip, bank, - bank->base + (i * chip->page_size), + bank->base + offset, buffer + (i * chip->page_size), 0, count); /* We're done after this. */ offset += count; @@ -627,21 +643,47 @@ static int sam4l_write(struct flash_bank *bank, uint8_t *buffer, return ERROR_OK; } -COMMAND_HANDLER(sam4l_handle_info_command) + +COMMAND_HANDLER(sam4l_handle_reset_deassert) { - return ERROR_OK; + struct target *target = get_current_target(CMD_CTX); + struct armv7m_common *armv7m = target_to_armv7m(target); + struct adiv5_dap *swjdp = armv7m->arm.dap; + int retval = ERROR_OK; + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset() + * so we just release reset held by SMAP + * + * n_RESET (srst) clears the DP, so reenable debug and set vector catch here + * + * After vectreset SMAP release is not needed however makes no harm + */ + if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) { + retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN); + if (retval == ERROR_OK) + retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, + TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET); + /* do not return on error here, releasing SMAP reset is more important */ + } + + int retval2 = mem_ap_write_atomic_u32(swjdp, SMAP_SCR, SMAP_SCR_HCR); + if (retval2 != ERROR_OK) + return retval2; + + return retval; } static const struct command_registration at91sam4l_exec_command_handlers[] = { { - .name = "info", - .handler = sam4l_handle_info_command, + .name = "smap_reset_deassert", + .handler = sam4l_handle_reset_deassert, .mode = COMMAND_EXEC, - .help = "Print information about the current at91sam4l chip" - "and its flash configuration.", + .help = "deasert internal reset held by SMAP" }, COMMAND_REGISTRATION_DONE }; + static const struct command_registration at91sam4l_command_handlers[] = { { .name = "at91sam4l",