X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91sam3.c;h=f895935fd9b756fd70ec75cea6430a761b6123d8;hp=0915ba7063d6479dd7cf1517453bfe086304fe81;hb=4df93cb95fd6ba7b8272b36ea7445657bbb66338;hpb=9629adcbde2bfac67296ad954c2233f725e1570e

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 0915ba7063..f895935fd9 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -1464,7 +1464,7 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 	v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
 	LOG_USER("(main osc bypass: %s)",
 				  _yes_or_no(v));
-	rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 2, 1);
+	rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
 	LOG_USER("(onchip RC-OSC enabled: %s)",
 				  _yes_or_no(rcen));
 	v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
@@ -1476,6 +1476,7 @@ sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 		switch (v) {
 		default:
 			pChip->cfg.rc_freq = 0;
+			break;
 		case 0:
 			pChip->cfg.rc_freq = 4 * 1000 * 1000;
 			break;
@@ -1628,6 +1629,7 @@ sam3_explain_mckr(struct sam3_chip *pChip)
 	case 0:
 		pdiv = 1;
 		cp = "selected clock";
+		break;
 	case 1:
 		pdiv = 2;
 		cp = "clock/2";