X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fdavinci_nand.c;h=72cd378a4da7fbd1b9bf331d77bc923a4a586d0c;hp=cab489f8d701c36d32e912e7f400ba73905897a6;hb=90d09e35e4be6f0b35899238b253154249f85cb6;hpb=c0fc8f93f1eabe8a4adfed7784b1416b257cf035 diff --git a/src/flash/davinci_nand.c b/src/flash/davinci_nand.c index cab489f8d7..72cd378a4d 100644 --- a/src/flash/davinci_nand.c +++ b/src/flash/davinci_nand.c @@ -28,7 +28,7 @@ #include "config.h" #endif -#include "nand.h" +#include "arm_nandio.h" enum ecc { @@ -38,24 +38,27 @@ enum ecc { }; struct davinci_nand { - target_t *target; + struct target *target; - u8 chipsel; /* chipselect 0..3 == CS2..CS5 */ - u8 eccmode; + uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */ + uint8_t eccmode; /* Async EMIF controller base */ - u32 aemif; + uint32_t aemif; /* NAND chip addresses */ - u32 data; /* without CLE or ALE */ - u32 cmd; /* with CLE */ - u32 addr; /* with ALE */ + uint32_t data; /* without CLE or ALE */ + uint32_t cmd; /* with CLE */ + uint32_t addr; /* with ALE */ + + /* write acceleration */ + struct arm_nand_data io; /* page i/o for the relevant flavor of hardware ECC */ - int (*read_page)(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size); - int (*write_page)(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size); + int (*read_page)(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size); + int (*write_page)(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size); }; #define NANDFCR 0x60 /* flash control register */ @@ -66,7 +69,7 @@ struct davinci_nand { #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */ #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */ -static int halted(target_t *target, const char *label) +static int halted(struct target *target, const char *label) { if (target->state == TARGET_HALTED) return true; @@ -75,16 +78,11 @@ static int halted(target_t *target, const char *label) return false; } -static int davinci_register_commands(struct command_context_s *cmd_ctx) -{ - return ERROR_OK; -} - -static int davinci_init(struct nand_device_s *nand) +static int davinci_init(struct nand_device *nand) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - u32 nandfcr; + struct target *target = info->target; + uint32_t nandfcr; if (!halted(target, "init")) return ERROR_NAND_OPERATION_FAILED; @@ -94,7 +92,7 @@ static int davinci_init(struct nand_device_s *nand) */ target_read_u32(target, info->aemif + NANDFCR, &nandfcr); if (!(nandfcr & (1 << info->chipsel))) { - LOG_ERROR("chip address %08x not NAND-enabled?", info->data); + LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data); return ERROR_NAND_OPERATION_FAILED; } @@ -105,16 +103,16 @@ static int davinci_init(struct nand_device_s *nand) return ERROR_OK; } -static int davinci_reset(struct nand_device_s *nand) +static int davinci_reset(struct nand_device *nand) { return ERROR_OK; } -static int davinci_nand_ready(struct nand_device_s *nand, int timeout) +static int davinci_nand_ready(struct nand_device *nand, int timeout) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - u32 nandfsr; + struct target *target = info->target; + uint32_t nandfsr; /* NOTE: return code is zero/error, else success; not ERROR_* */ @@ -133,10 +131,10 @@ static int davinci_nand_ready(struct nand_device_s *nand, int timeout) return 0; } -static int davinci_command(struct nand_device_s *nand, u8 command) +static int davinci_command(struct nand_device *nand, uint8_t command) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; + struct target *target = info->target; if (!halted(target, "command")) return ERROR_NAND_OPERATION_FAILED; @@ -145,10 +143,10 @@ static int davinci_command(struct nand_device_s *nand, u8 command) return ERROR_OK; } -static int davinci_address(struct nand_device_s *nand, u8 address) +static int davinci_address(struct nand_device *nand, uint8_t address) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; + struct target *target = info->target; if (!halted(target, "address")) return ERROR_NAND_OPERATION_FAILED; @@ -157,10 +155,10 @@ static int davinci_address(struct nand_device_s *nand, u8 address) return ERROR_OK; } -static int davinci_write_data(struct nand_device_s *nand, u16 data) +static int davinci_write_data(struct nand_device *nand, uint16_t data) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; + struct target *target = info->target; if (!halted(target, "write_data")) return ERROR_NAND_OPERATION_FAILED; @@ -169,10 +167,10 @@ static int davinci_write_data(struct nand_device_s *nand, u16 data) return ERROR_OK; } -static int davinci_read_data(struct nand_device_s *nand, void *data) +static int davinci_read_data(struct nand_device *nand, void *data) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; + struct target *target = info->target; if (!halted(target, "read_data")) return ERROR_NAND_OPERATION_FAILED; @@ -181,15 +179,15 @@ static int davinci_read_data(struct nand_device_s *nand, void *data) return ERROR_OK; } -/* REVISIT a bit of native code should let block I/O be MUCH faster */ +/* REVISIT a bit of native code should let block reads be MUCH faster */ -static int davinci_read_block_data(struct nand_device_s *nand, - u8 *data, int data_size) +static int davinci_read_block_data(struct nand_device *nand, + uint8_t *data, int data_size) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - u32 nfdata = info->data; - u32 tmp; + struct target *target = info->target; + uint32_t nfdata = info->data; + uint32_t tmp; if (!halted(target, "read_block")) return ERROR_NAND_OPERATION_FAILED; @@ -216,17 +214,24 @@ static int davinci_read_block_data(struct nand_device_s *nand, return ERROR_OK; } -static int davinci_write_block_data(struct nand_device_s *nand, - u8 *data, int data_size) +static int davinci_write_block_data(struct nand_device *nand, + uint8_t *data, int data_size) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - u32 nfdata = info->data; - u32 tmp; + struct target *target = info->target; + uint32_t nfdata = info->data; + uint32_t tmp; + int status; if (!halted(target, "write_block")) return ERROR_NAND_OPERATION_FAILED; + /* try the fast way first */ + status = arm_nandwrite(&info->io, data, data_size); + if (status != ERROR_NAND_NO_BUFFER) + return status; + + /* else do it slowly */ while (data_size >= 4) { tmp = le_to_h_u32(data); target_write_u32(target, nfdata, tmp); @@ -245,11 +250,11 @@ static int davinci_write_block_data(struct nand_device_s *nand, return ERROR_OK; } -static int davinci_write_page(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_write_page(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { struct davinci_nand *info = nand->controller_priv; - u8 *ooballoc = NULL; + uint8_t *ooballoc = NULL; int status; if (!nand->device) @@ -258,8 +263,10 @@ static int davinci_write_page(struct nand_device_s *nand, u32 page, return ERROR_NAND_OPERATION_FAILED; /* Always write both data and OOB ... we are not "raw" I/O! */ - if (!data) + if (!data) { + LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n"); return ERROR_NAND_OPERATION_FAILED; + } /* If we're not given OOB, write 0xff where we don't write ECC codes. */ switch (nand->page_size) { @@ -277,19 +284,25 @@ static int davinci_write_page(struct nand_device_s *nand, u32 page, } if (!oob) { ooballoc = malloc(oob_size); - if (ooballoc) + if (!ooballoc) return ERROR_NAND_OPERATION_FAILED; oob = ooballoc; memset(oob, 0x0ff, oob_size); } + /* REVISIT avoid wasting SRAM: unless nand->use_raw is set, + * use 512 byte chunks. Read side support will often want + * to include oob_size ... + */ + info->io.chunk_size = nand->page_size; + status = info->write_page(nand, page, data, data_size, oob, oob_size); free(ooballoc); return status; } -static int davinci_read_page(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_read_page(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { struct davinci_nand *info = nand->controller_priv; @@ -301,10 +314,10 @@ static int davinci_read_page(struct nand_device_s *nand, u32 page, return info->read_page(nand, page, data, data_size, oob, oob_size); } -static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page) +static void davinci_write_pagecmd(struct nand_device *nand, uint8_t cmd, uint32_t page) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; + struct target *target = info->target; int page3 = nand->address_cycles - (nand->page_size == 512); /* write command ({page,otp}x{read,program} */ @@ -324,12 +337,12 @@ static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page) target_write_u8(target, info->addr, page >> 24); } -static int davinci_writepage_tail(struct nand_device_s *nand, - u8 *oob, u32 oob_size) +static int davinci_writepage_tail(struct nand_device *nand, + uint8_t *oob, uint32_t oob_size) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - u8 status; + struct target *target = info->target; + uint8_t status; if (oob_size) davinci_write_block_data(nand, oob, oob_size); @@ -356,15 +369,15 @@ static int davinci_writepage_tail(struct nand_device_s *nand, /* * All DaVinci family chips support 1-bit ECC on a per-chipselect basis. */ -static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_write_page_ecc1(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { unsigned oob_offset; struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - const u32 fcr_addr = info->aemif + NANDFCR; - const u32 ecc1_addr = info->aemif + NANDFECC + info->chipsel; - u32 fcr, ecc1; + struct target *target = info->target; + const uint32_t fcr_addr = info->aemif + NANDFCR; + const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel); + uint32_t fcr, ecc1; /* Write contiguous ECC bytes starting at specified offset. * NOTE: Linux reserves twice as many bytes as we need; and @@ -407,9 +420,9 @@ static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page, ecc1 = ~ecc1; /* save correct ECC code into oob data */ - oob[oob_offset++] = (u8)(ecc1); - oob[oob_offset++] = (u8)(ecc1 >> 8); - oob[oob_offset++] = (u8)(ecc1 >> 16); + oob[oob_offset++] = (uint8_t)(ecc1); + oob[oob_offset++] = (uint8_t)(ecc1 >> 8); + oob[oob_offset++] = (uint8_t)(ecc1 >> 16); } while (data_size); @@ -423,20 +436,20 @@ static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page, * is read first, so its ECC data can be used incrementally), but the * manufacturer bad block markers are safe. Contrast: old "infix" style. */ -static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_write_page_ecc4(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { - static const u8 ecc512[] = { + static const uint8_t ecc512[] = { 0, 1, 2, 3, 4, /* 5== mfr badblock */ 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15, }; - static const u8 ecc2048[] = { + static const uint8_t ecc2048[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, }; - static const u8 ecc4096[] = { + static const uint8_t ecc4096[] = { 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, @@ -448,11 +461,11 @@ static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page, }; struct davinci_nand *info = nand->controller_priv; - const u8 *l; - target_t *target = info->target; - const u32 fcr_addr = info->aemif + NANDFCR; - const u32 ecc4_addr = info->aemif + NAND4BITECC; - u32 fcr, ecc4; + const uint8_t *l; + struct target *target = info->target; + const uint32_t fcr_addr = info->aemif + NANDFCR; + const uint32_t ecc4_addr = info->aemif + NAND4BITECC; + uint32_t fcr, ecc4; /* Use the same ECC layout Linux uses. For small page chips * it's a bit cramped. @@ -483,7 +496,7 @@ static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page, fcr |= (1 << 12) | (info->chipsel << 4); do { - u32 raw_ecc[4], *p; + uint32_t raw_ecc[4], *p; int i; /* start 4bit ecc on csX */ @@ -525,14 +538,14 @@ static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page, * older second stage loaders (ABL/U-Boot, etc) or other system software * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally. */ -static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_write_page_ecc4infix(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { struct davinci_nand *info = nand->controller_priv; - target_t *target = info->target; - const u32 fcr_addr = info->aemif + NANDFCR; - const u32 ecc4_addr = info->aemif + NAND4BITECC; - u32 fcr, ecc4; + struct target *target = info->target; + const uint32_t fcr_addr = info->aemif + NANDFCR; + const uint32_t ecc4_addr = info->aemif + NAND4BITECC; + uint32_t fcr, ecc4; davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page); @@ -544,8 +557,8 @@ static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page, fcr |= (1 << 12) | (info->chipsel << 4); do { - u32 raw_ecc[4], *p; - u8 *l; + uint32_t raw_ecc[4], *p; + uint8_t *l; int i; /* start 4bit ecc on csX */ @@ -582,8 +595,8 @@ static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page, return davinci_writepage_tail(nand, NULL, 0); } -static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page, - u8 *data, u32 data_size, u8 *oob, u32 oob_size) +static int davinci_read_page_ecc4infix(struct nand_device *nand, uint32_t page, + uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size) { davinci_write_pagecmd(nand, NAND_CMD_READ0, page); @@ -611,16 +624,13 @@ static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page, return ERROR_OK; } -static int davinci_nand_device_command(struct command_context_s *cmd_ctx, - char *cmd, char **argv, int argc, - struct nand_device_s *nand) +NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command) { struct davinci_nand *info; - target_t *target; + struct target *target; unsigned long chip, aemif; enum ecc eccmode; int chipsel; - char *ep; /* arguments: * - "davinci" @@ -630,39 +640,39 @@ static int davinci_nand_device_command(struct command_context_s *cmd_ctx, * - aemif address * Plus someday, optionally, ALE and CLE masks. */ - if (argc < 5) { + if (CMD_ARGC < 5) { LOG_ERROR("parameters: %s target " "chip_addr hwecc_mode aemif_addr", - argv[0]); + CMD_ARGV[0]); goto fail; } - target = get_target(argv[1]); + target = get_target(CMD_ARGV[1]); if (!target) { - LOG_ERROR("invalid target %s", argv[1]); + LOG_ERROR("invalid target %s", CMD_ARGV[1]); goto fail; } - chip = strtoul(argv[2], &ep, 0); - if (*ep || chip == 0 || chip == ULONG_MAX) { - LOG_ERROR("Invalid NAND chip address %s", argv[2]); + COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip); + if (chip == 0) { + LOG_ERROR("Invalid NAND chip address %s", CMD_ARGV[2]); goto fail; } - if (strcmp(argv[3], "hwecc1") == 0) + if (strcmp(CMD_ARGV[3], "hwecc1") == 0) eccmode = HWECC1; - else if (strcmp(argv[3], "hwecc4") == 0) + else if (strcmp(CMD_ARGV[3], "hwecc4") == 0) eccmode = HWECC4; - else if (strcmp(argv[3], "hwecc4_infix") == 0) + else if (strcmp(CMD_ARGV[3], "hwecc4_infix") == 0) eccmode = HWECC4_INFIX; else { - LOG_ERROR("Invalid ecc mode %s", argv[3]); + LOG_ERROR("Invalid ecc mode %s", CMD_ARGV[3]); goto fail; } - aemif = strtoul(argv[4], &ep, 0); - if (*ep || chip == 0 || chip == ULONG_MAX) { - LOG_ERROR("Invalid AEMIF controller address %s", argv[4]); + COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[4], aemif); + if (aemif == 0) { + LOG_ERROR("Invalid AEMIF controller address %s", CMD_ARGV[4]); goto fail; } @@ -674,11 +684,11 @@ static int davinci_nand_device_command(struct command_context_s *cmd_ctx, || aemif == 0x01e10000 /* dm335, dm355 */ || aemif == 0x01d10000 /* dm365 */ ) { - if (chip < 0x0200000 || chip >= 0x0a000000) { + if (chip < 0x02000000 || chip >= 0x0a000000) { LOG_ERROR("NAND address %08lx out of range?", chip); goto fail; } - chipsel = (chip - 0x02000000) >> 21; + chipsel = (chip - 0x02000000) >> 25; } else { LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif); goto fail; @@ -698,6 +708,9 @@ static int davinci_nand_device_command(struct command_context_s *cmd_ctx, nand->controller_priv = info; + info->io.target = target; + info->io.data = info->data; + /* NOTE: for now we don't do any error correction on read. * Nothing else in OpenOCD currently corrects read errors, * and in any case it's *writing* that we care most about. @@ -726,10 +739,9 @@ fail: return ERROR_NAND_OPERATION_FAILED; } -nand_flash_controller_t davinci_nand_controller = { +struct nand_flash_controller davinci_nand_controller = { .name = "davinci", .nand_device_command = davinci_nand_device_command, - .register_commands = davinci_register_commands, .init = davinci_init, .reset = davinci_reset, .command = davinci_command,