X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=fd92d51acfcca70ac993859f1e866cdc9032b378;hp=48297abfb2d70eeb310523d2ee8a4833be204d5e;hb=ff640f197a9a343b2f3ed10e9174e35282334e8c;hpb=952de89bfeac60bdca55add6ef0f7835ae00e66a

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 48297abfb2..fd92d51acf 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1679,6 +1679,64 @@ Again using the at91sam7 as an example, this can look like:
 $_TARGETNAME configure -work-area-phys 0x00200000 \
              -work-area-size 0x4000 -work-area-backup 0
 @end example
+@pxref{Define CPU targets working in SMP}
+@anchor{Define CPU targets working in SMP}
+@subsection Define CPU targets working in SMP
+@cindex SMP
+After setting targets, you can define a list of targets working in SMP.
+
+@example 
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+set _TARGETNAME_2 $_CHIPNAME.cpu2
+target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
+-coreid 0 -dbgbase $_DAP_DBG1 
+target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
+-coreid 1 -dbgbase $_DAP_DBG2 
+#define 2 targets working in smp. 
+target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
+@end example
+In the above example on cortex_a8, 2 cpus are working in SMP.
+In SMP only one GDB instance is created and :
+@itemize @bullet
+@item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
+@item halt command triggers the halt of all targets in the list.
+@item resume command triggers the write context and the restart of all targets in the list.
+@item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session.
+@item dedicated GDB serial protocol packets are implemented for switching/retrieving the target 
+displayed by the GDB session @pxref{Using openocd SMP with GDB}.
+@end itemize
+
+The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
+command have been implemented.
+@itemize @bullet
+@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
+@item cortex_a8 smp_off : disable SMP mode, the current target is the one
+displayed in the GDB session, only this target is now controlled by GDB
+session. This behaviour is useful during system boot up.
+@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
+following example.
+@end itemize
+
+@example
+>cortex_a8 smp_gdb
+gdb coreid  0 -> -1  
+#0 : coreid 0 is displayed to GDB ,
+#-> -1 : next resume triggers a real resume
+> cortex_a8 smp_gdb 1
+gdb coreid  0 -> 1   
+#0 :coreid 0 is displayed to GDB ,
+#->1  : next resume displays coreid 1 to GDB 
+> resume
+> cortex_a8 smp_gdb  
+gdb coreid  1 -> 1
+#1 :coreid 1 is displayed to GDB ,
+#->1 : next resume displays coreid 1 to GDB
+> cortex_a8 smp_gdb -1
+gdb coreid  1 -> -1
+#1 :coreid 1 is displayed to GDB,
+#->-1 : next resume triggers a real resume
+@end example
+
 
 @subsection Chip Reset Setup
 
@@ -2321,6 +2379,24 @@ This is a write-once setting.
 Segger jlink USB adapter
 @c command:	jlink caps
 @c     dumps jlink capabilities
+@c command:	jlink config
+@c     access J-Link configurationif no argument this will dump the config
+@c command:	jlink config kickstart [val]
+@c     set Kickstart power on JTAG-pin 19.
+@c command:	jlink config mac_address [ff:ff:ff:ff:ff:ff]
+@c     set the MAC Address
+@c command:	jlink config ip [A.B.C.D[/E] [F.G.H.I]]
+@c     set the ip address of the J-Link Pro, "
+@c     where A.B.C.D is the ip,
+@c     E the bit of the subnet mask
+@c     F.G.H.I the subnet mask
+@c command:	jlink config reset
+@c     reset the current config
+@c command:	jlink config save
+@c     save the current config
+@c command:	jlink config usb_address [0x00 to 0x03 or 0xff]
+@c     set the USB-Address,
+@c     This will change the product id
 @c command:	jlink info
 @c     dumps status
 @c command:	jlink hw_jtag (2|3)
@@ -5770,7 +5846,7 @@ Loads an image stored in memory by @command{fast_load_image} to the
 current target. Must be preceeded by fast_load_image.
 @end deffn
 
-@deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}]
+@deffn Command {fast_load_image} filename address [@option{bin}|@option{ihex}|@option{elf}|@option{s19}]
 Normally you should be using @command{load_image} or GDB load. However, for
 testing purposes or when I/O overhead is significant(OpenOCD running on an embedded
 host), storing the image in memory and uploading the image to the target
@@ -5782,10 +5858,10 @@ separately.
 @end deffn
 
 @anchor{load_image}
-@deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}] @option{min_addr} @option{max_length}]
+@deffn Command {load_image} filename address [[@option{bin}|@option{ihex}|@option{elf}|@option{s19}] @option{min_addr} @option{max_length}]
 Load image from file @var{filename} to target memory offset by @var{address} from its load address. 
 The file format may optionally be specified
-(@option{bin}, @option{ihex}, or @option{elf}).
+(@option{bin}, @option{ihex}, @option{elf}, or @option{s19}).
 In addition the following arguments may be specifed:
 @var{min_addr} - ignore data below @var{min_addr} (this is w.r.t. to the target's load address + @var{address})
 @var{max_length} - maximum number of bytes to load.
@@ -6644,8 +6720,21 @@ If @var{value} is defined, first assigns that.
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3
 
-@deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
+@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off})
 Control masking (disabling) interrupts during target step/resume.
+
+The @option{auto} option handles interrupts during stepping a way they get
+served but don't disturb the program flow. The step command first allows
+pending interrupt handlers to execute, then disables interrupts and steps over
+the next instruction where the core was halted. After the step interrupts
+are enabled again. If the interrupt handlers don't complete within 500ms,
+the step command leaves with the core running.
+
+Note that a free breakpoint is required for the @option{auto} option. If no
+breakpoint is available at the time of the step, then the step is taken
+with interrupts enabled, i.e. the same way the @option{off} option does.
+
+Default is @option{auto}.
 @end deffn
 
 @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
@@ -7257,6 +7346,55 @@ $_TARGETNAME configure -event EVENTNAME BODY
 
 To verify any flash programming the GDB command @option{compare-sections}
 can be used.
+@anchor{Using openocd SMP with GDB}
+@section Using openocd SMP with GDB
+@cindex SMP
+For SMP support following GDB serial protocol packet have been defined :
+@itemize @bullet
+@item j - smp status request 
+@item J - smp set request
+@end itemize
+
+OpenOCD implements :
+@itemize @bullet
+@item @option{jc} packet for reading core id displayed by
+GDB connection. Reply is  @option{XXXXXXXX} (8 hex digits giving core id) or
+ @option{E01} for target not smp.
+@item  @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue 
+(core id -1 is reserved for returning to normal resume mode). Reply  @option{E01} 
+for target not smp or @option{OK} on success.
+@end itemize
+
+Handling of this packet within GDB can be done :
+@itemize @bullet
+@item by the creation of an internal variable (i.e @option{_core}) by mean 
+of function allocate_computed_value allowing following GDB command.
+@example
+set $_core 1 
+#Jc01 packet is sent
+print $_core 
+#jc packet is sent and result is affected in $ 
+@end example
+
+@item by the usage of GDB maintenance command as described in following example (2
+cpus in SMP with core id 0 and 1  @pxref{Define CPU targets working in SMP}).
+
+@example
+# toggle0 : force display of coreid 0 
+define toggle0 
+maint packet Jc0 
+continue 
+main packet Jc-1 
+end 
+# toggle1 : force display of coreid 1 
+define toggle1 
+maint packet Jc1 
+continue 
+main packet Jc-1 
+end 
+@end example
+@end itemize
+
 
 @node Tcl Scripting API
 @chapter Tcl Scripting API