X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=dfb8e30da950d9ada7c0cad1cb03515346b1fbc9;hp=2c09febd94e4a383a9f33ff4b456218ccba509a0;hb=1cfd3fdda9dc706f002be5e8a1461a82b73ff1f5;hpb=3b7c9585db2dd49b48123d50e9e8af7bc527be52;ds=sidebyside diff --git a/doc/openocd.texi b/doc/openocd.texi index 2c09febd94..dfb8e30da9 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -526,7 +526,7 @@ OpenOCD mailing list. @item @b{Jim vs. Tcl} @* Jim-Tcl is a stripped down version of the well known Tcl language, which can be found here: @url{http://www.tcl.tk}. Jim-Tcl has far -fewer features. Jim-Tcl is a single .C file and a single .H file and +fewer features. Jim-Tcl is several dozens of .C files and .H files and implements the basic Tcl command set. In contrast: Tcl 8.6 is a 4.2 MB .zip file containing 1540 files. @@ -676,8 +676,6 @@ setting from within a telnet or gdb session using @command{debug_level You can redirect all output from the daemon to a file using the @option{-l } switch. -For details on the @option{-p} option. @xref{Connecting to GDB}. - Note! OpenOCD will launch the GDB & telnet server even if it can not establish a connection with the target. In general, it is possible for the JTAG controller to be unresponsive until the target is set up @@ -1679,6 +1677,64 @@ Again using the at91sam7 as an example, this can look like: $_TARGETNAME configure -work-area-phys 0x00200000 \ -work-area-size 0x4000 -work-area-backup 0 @end example +@pxref{Define CPU targets working in SMP} +@anchor{Define CPU targets working in SMP} +@subsection Define CPU targets working in SMP +@cindex SMP +After setting targets, you can define a list of targets working in SMP. + +@example +set _TARGETNAME_1 $_CHIPNAME.cpu1 +set _TARGETNAME_2 $_CHIPNAME.cpu2 +target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \ +-coreid 0 -dbgbase $_DAP_DBG1 +target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \ +-coreid 1 -dbgbase $_DAP_DBG2 +#define 2 targets working in smp. +target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1 +@end example +In the above example on cortex_a8, 2 cpus are working in SMP. +In SMP only one GDB instance is created and : +@itemize @bullet +@item a set of hardware breakpoint sets the same breakpoint on all targets in the list. +@item halt command triggers the halt of all targets in the list. +@item resume command triggers the write context and the restart of all targets in the list. +@item following a breakpoint: the target stopped by the breakpoint is displayed to the GDB session. +@item dedicated GDB serial protocol packets are implemented for switching/retrieving the target +displayed by the GDB session @pxref{Using openocd SMP with GDB}. +@end itemize + +The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following +command have been implemented. +@itemize @bullet +@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above. +@item cortex_a8 smp_off : disable SMP mode, the current target is the one +displayed in the GDB session, only this target is now controlled by GDB +session. This behaviour is useful during system boot up. +@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see +following example. +@end itemize + +@example +>cortex_a8 smp_gdb +gdb coreid 0 -> -1 +#0 : coreid 0 is displayed to GDB , +#-> -1 : next resume triggers a real resume +> cortex_a8 smp_gdb 1 +gdb coreid 0 -> 1 +#0 :coreid 0 is displayed to GDB , +#->1 : next resume displays coreid 1 to GDB +> resume +> cortex_a8 smp_gdb +gdb coreid 1 -> 1 +#1 :coreid 1 is displayed to GDB , +#->1 : next resume displays coreid 1 to GDB +> cortex_a8 smp_gdb -1 +gdb coreid 1 -> -1 +#1 :coreid 1 is displayed to GDB, +#->-1 : next resume triggers a real resume +@end example + @subsection Chip Reset Setup @@ -4826,6 +4882,19 @@ flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME @end example @end deffn +@deffn {Flash Driver} fm3 +All members of the FM3 microcontroller family from Fujitsu +include internal flash and use ARM Cortex M3 cores. +The @var{fm3} driver uses the @var{target} parameter to select the +correct bank config, it can currently be one of the following: +@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu}, +@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}. + +@example +flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME +@end example +@end deffn + @subsection str9xpec driver @cindex str9xpec @@ -6662,8 +6731,21 @@ If @var{value} is defined, first assigns that. @subsection Cortex-M3 specific commands @cindex Cortex-M3 -@deffn Command {cortex_m3 maskisr} (@option{on}|@option{off}) +@deffn Command {cortex_m3 maskisr} (@option{auto}|@option{on}|@option{off}) Control masking (disabling) interrupts during target step/resume. + +The @option{auto} option handles interrupts during stepping a way they get +served but don't disturb the program flow. The step command first allows +pending interrupt handlers to execute, then disables interrupts and steps over +the next instruction where the core was halted. After the step interrupts +are enabled again. If the interrupt handlers don't complete within 500ms, +the step command leaves with the core running. + +Note that a free breakpoint is required for the @option{auto} option. If no +breakpoint is available at the time of the step, then the step is taken +with interrupts enabled, i.e. the same way the @option{off} option does. + +Default is @option{auto}. @end deffn @deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list] @@ -7275,6 +7357,55 @@ $_TARGETNAME configure -event EVENTNAME BODY To verify any flash programming the GDB command @option{compare-sections} can be used. +@anchor{Using openocd SMP with GDB} +@section Using openocd SMP with GDB +@cindex SMP +For SMP support following GDB serial protocol packet have been defined : +@itemize @bullet +@item j - smp status request +@item J - smp set request +@end itemize + +OpenOCD implements : +@itemize @bullet +@item @option{jc} packet for reading core id displayed by +GDB connection. Reply is @option{XXXXXXXX} (8 hex digits giving core id) or + @option{E01} for target not smp. +@item @option{JcXXXXXXXX} (8 hex digits) packet for setting core id displayed at next GDB continue +(core id -1 is reserved for returning to normal resume mode). Reply @option{E01} +for target not smp or @option{OK} on success. +@end itemize + +Handling of this packet within GDB can be done : +@itemize @bullet +@item by the creation of an internal variable (i.e @option{_core}) by mean +of function allocate_computed_value allowing following GDB command. +@example +set $_core 1 +#Jc01 packet is sent +print $_core +#jc packet is sent and result is affected in $ +@end example + +@item by the usage of GDB maintenance command as described in following example (2 +cpus in SMP with core id 0 and 1 @pxref{Define CPU targets working in SMP}). + +@example +# toggle0 : force display of coreid 0 +define toggle0 +maint packet Jc0 +continue +main packet Jc-1 +end +# toggle1 : force display of coreid 1 +define toggle1 +maint packet Jc1 +continue +main packet Jc-1 +end +@end example +@end itemize + @node Tcl Scripting API @chapter Tcl Scripting API