X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=c5a926ca86b5e3a8b7d4075f3451fbfe1d58fd5e;hp=4fb7b00b16fec62e1b4d1642d592e77b4d80ee88;hb=5a235226f0db67e85f9c71288dcd015e7081c37b;hpb=24bfdf53fdb3f79dd6ef4c435feee5d94ab85a19 diff --git a/doc/openocd.texi b/doc/openocd.texi index 4fb7b00b16..c5a926ca86 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -2370,8 +2370,8 @@ Returns the name of the debug adapter driver being used. @end deffn @anchor{adapter_usb_location} -@deffn Command {adapter usb location} -[.]... -Specifies the physical USB port of the adapter to use. The path +@deffn Command {adapter usb location} [-[.]...] +Displays or specifies the physical USB port of the adapter to use. The path roots at @var{bus} and walks down the physical ports, with each @var{port} option specifying a deeper level in the bus topology, the last @var{port} denoting where the target adapter is actually plugged. @@ -3479,7 +3479,7 @@ How long (in milliseconds) OpenOCD should wait after deasserting nTRST (active-low JTAG TAP reset) before starting new JTAG operations. @end deffn -@anchor {reset_config} +@anchor{reset_config} @deffn {Command} reset_config mode_flag ... This command displays or modifies the reset configuration of your combination of JTAG board and target in target @@ -7002,6 +7002,23 @@ unlock str9 device. @end deffn +@deffn {Flash Driver} swm050 +@cindex swm050 +All members of the swm050 microcontroller family from Foshan Synwit Tech. + +@example +flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME +@end example + +One swm050-specific command is defined: + +@deffn Command {swm050 mass_erase} bank_id +Erases the entire flash bank. +@end deffn + +@end deffn + + @deffn {Flash Driver} tms470 Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. @@ -7482,67 +7499,6 @@ or @code{read_page} methods, so @command{nand raw_access} won't change any behavior. @end deffn -@section mFlash - -@subsection mFlash Configuration -@cindex mFlash Configuration - -@deffn {Config Command} {mflash bank} soc base RST_pin target -Configures a mflash for @var{soc} host bank at -address @var{base}. -The pin number format depends on the host GPIO naming convention. -Currently, the mflash driver supports s3c2440 and pxa270. - -Example for s3c2440 mflash where @var{RST pin} is GPIO B1: - -@example -mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0 -@end example - -Example for pxa270 mflash where @var{RST pin} is GPIO 43: - -@example -mflash bank $_FLASHNAME pxa270 0x08000000 43 0 -@end example -@end deffn - -@subsection mFlash commands -@cindex mFlash commands - -@deffn Command {mflash config pll} frequency -Configure mflash PLL. -The @var{frequency} is the mflash input frequency, in Hz. -Issuing this command will erase mflash's whole internal nand and write new pll. -After this command, mflash needs power-on-reset for normal operation. -If pll was newly configured, storage and boot(optional) info also need to be update. -@end deffn - -@deffn Command {mflash config boot} -Configure bootable option. -If bootable option is set, mflash offer the first 8 sectors -(4kB) for boot. -@end deffn - -@deffn Command {mflash config storage} -Configure storage information. -For the normal storage operation, this information must be -written. -@end deffn - -@deffn Command {mflash dump} num filename offset size -Dump @var{size} bytes, starting at @var{offset} bytes from the -beginning of the bank @var{num}, to the file named @var{filename}. -@end deffn - -@deffn Command {mflash probe} -Probe mflash. -@end deffn - -@deffn Command {mflash write} num filename offset -Write the binary file @var{filename} to mflash bank @var{num}, starting at -@var{offset} bytes from the beginning of the bank. -@end deffn - @node Flash Programming @chapter Flash Programming @@ -9190,6 +9146,14 @@ Selects whether interrupts will be processed when single stepping. The default c @option{on}. @end deffn +@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+ +Cause @command{$target_name} to halt when an exception is taken. Any combination of +Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target +@command{$target_name} will halt before taking the exception. In order to resume +the target, the exception catch must be disabled again with @command{$target_name catch_exc off}. +Issuing the command without options prints the current configuration. +@end deffn + @section EnSilica eSi-RISC Architecture eSi-RISC is a highly configurable microprocessor architecture for embedded systems @@ -9333,7 +9297,7 @@ collection. @deffn Command {esirisc trace init} Initialize trace collection. This command must be called any time the -configuration changes. If an trace buffer has been configured, the contents will +configuration changes. If a trace buffer has been configured, the contents will be overwritten when trace collection starts. @end deffn @@ -9367,14 +9331,6 @@ be copied to an in-memory buffer identified by the @option{address} and @option{size} options using DMA. @end deffn -@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+ -Cause @command{$target_name} to halt when an exception is taken. Any combination of -Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target -@command{$target_name} will halt before taking the exception. In order to resume -the target, the exception catch must be disabled again with @command{$target_name catch_exc off}. -Issuing the command without options prints the current configuration. -@end deffn - @section Intel Architecture Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32