X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=98fc6900709a11973bedab77acd48128c4211ea1;hp=e1bb2b770892b7ae2e4ddebcb51cb5b1a98d3ee1;hb=3ad171cd537f8fc1bac649f24513ebfafd95baf2;hpb=1bd3ae398646da1107e00e0651abbf9691d2d9ff

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e1bb2b7708..98fc690070 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -590,6 +590,7 @@ Configuration files and scripts are searched for in
 @enumerate
 @item the current directory,
 @item any search dir specified on the command line using the @option{-s} option,
+@item any search dir specified using the @command{add_script_search_dir} command,
 @item @file{$HOME/.openocd} (not on Windows),
 @item the site wide script library @file{$pkgdatadir/site} and
 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
@@ -3453,14 +3454,6 @@ be detected and the normal reset behaviour used.
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
 @item @code{mips_m4k} -- a MIPS core.  This supports one variant:
-@itemize @minus
-@item @code{ejtag_srst} ... Use this when debugging targets that do not
-provide a functional SRST line on the EJTAG connector.  This causes
-OpenOCD to instead use an EJTAG software reset command to reset the
-processor.
-You still need to enable @option{srst} on the @command{reset_config}
-command to enable OpenOCD hardware reset functionality.
-@end itemize
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type.  It is based on the ARMv5 architecture.
 There are several variants defined:
@@ -5404,6 +5397,10 @@ Redirect logging to @var{filename};
 the initial log output channel is stderr.
 @end deffn
 
+@deffn Command add_script_search_dir [directory]
+Add @var{directory} to the file/script search path.
+@end deffn
+
 @anchor{Target State handling}
 @section Target State handling
 @cindex reset