X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=5a1e095663bcdb0cf0893125bd1472f9d913863d;hp=93757d48ff34394696927ff8aa189da9f53abf61;hb=96f9790279f74f39b35fc3ad09340fd03123180c;hpb=4b964a81ca1423b808a056b457e3d458689d50fa

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 93757d48ff..5a1e095663 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1516,7 +1516,7 @@ solution just avoids using that instruction with JTAG debuggers.
 If both the chip and the board support adaptive clocking,
 use the @command{jtag_rclk}
 command, in case your board is used with JTAG adapter which
-also supports it.  Otherwise use @command{jtag_khz}.
+also supports it.  Otherwise use @command{adapter_khz}.
 Set the slow rate at the beginning of the reset sequence,
 and the faster rate as soon as the clocks are at full speed.
 
@@ -2342,7 +2342,7 @@ you may encounter a problem.
 @deffn Command {parport_toggling_time} [nanoseconds]
 Displays how many nanoseconds the hardware needs to toggle TCK;
 the parport driver uses this value to obey the
-@command{jtag_khz} configuration.
+@command{adapter_khz} configuration.
 When the optional @var{nanoseconds} parameter is given,
 that setting is changed before displaying the current value.
 
@@ -2353,7 +2353,7 @@ To measure the toggling time with a logic analyzer or a digital storage
 oscilloscope, follow the procedure below:
 @example
 > parport_toggling_time 1000
-> jtag_khz 500
+> adapter_khz 500
 @end example
 This sets the maximum JTAG clock speed of the hardware, but
 the actual speed probably deviates from the requested 500 kHz.
@@ -2364,14 +2364,14 @@ Update the setting to match your measurement:
 @example
 > parport_toggling_time <measured nanoseconds>
 @end example
-Now the clock speed will be a better match for @command{jtag_khz rate}
+Now the clock speed will be a better match for @command{adapter_khz rate}
 commands given in OpenOCD scripts and event handlers.
 
 You can do something similar with many digital multimeters, but note
 that you'll probably need to run the clock continuously for several
 seconds before it decides what clock rate to show.  Adjust the
 toggling time up or down until the measured clock rate is a good
-match for the jtag_khz rate you specified; be conservative.
+match for the adapter_khz rate you specified; be conservative.
 @end quotation
 @end deffn
 
@@ -2470,10 +2470,10 @@ However, it introduces delays to synchronize clocks; so it
 may not be the fastest solution.
 
 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
-instead of @command{jtag_khz}, but only for (ARM) cores and boards
+instead of @command{adapter_khz}, but only for (ARM) cores and boards
 which support adaptive clocking.
 
-@deffn {Command} jtag_khz max_speed_kHz
+@deffn {Command} adapter_khz max_speed_kHz
 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.
 JTAG interfaces usually support a limited number of
 speeds.  The speed actually used won't be faster
@@ -3881,7 +3881,7 @@ the target clocks are fully set up.)
 before @command{reset_init} is called.
 
 This is the most robust place to use @command{jtag_rclk}
-or @command{jtag_khz} to switch to a low JTAG clock rate,
+or @command{adapter_khz} to switch to a low JTAG clock rate,
 when reset disables PLLs needed to use a fast clock.
 @ignore
 @item @b{reset-wait-pos}
@@ -7290,7 +7290,7 @@ To set the JTAG frequency use the command:
 
 @example
 # Example: 1.234MHz
-jtag_khz 1234
+adapter_khz 1234
 @end example