X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=349998b3599074b47f90b69c3946fdb2a00e7561;hp=57d1b09591cd0327f00df3737243c882b16fb52f;hb=0750a7c085b0fb8b195b210a6835c93ea88a19f3;hpb=11e5f022760a8ba497f41d0625d5757c313dc038 diff --git a/doc/openocd.texi b/doc/openocd.texi index 57d1b09591..349998b359 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -3479,7 +3479,7 @@ How long (in milliseconds) OpenOCD should wait after deasserting nTRST (active-low JTAG TAP reset) before starting new JTAG operations. @end deffn -@anchor {reset_config} +@anchor{reset_config} @deffn {Command} reset_config mode_flag ... This command displays or modifies the reset configuration of your combination of JTAG board and target in target @@ -4949,6 +4949,20 @@ flash drivers can distinguish between probing and autoprobing, but most don't bother. @end deffn +@section Preparing a Target before Flash Programming + +The target device should be in well defined state before the flash programming +begins. + +@emph{Always issue} @command{reset init} before @ref{flashprogrammingcommands,,Flash Programming Commands}. +Do not issue another @command{reset} or @command{reset halt} or @command{resume} +until the programming session is finished. + +If you use @ref{programmingusinggdb,,Programming using GDB}, +the target is prepared automatically in the event gdb-flash-erase-start + +The jimtcl script @command{program} calls @command{reset init} explicitly. + @section Erasing, Reading, Writing to Flash @cindex flash erasing @cindex flash reading @@ -5124,7 +5138,7 @@ command or the flash driver then it defaults to 0xff. @end deffn @anchor{program} -@deffn Command {program} filename [verify] [reset] [exit] [offset] +@deffn Command {program} filename [preverify] [verify] [reset] [exit] [offset] This is a helper script that simplifies using OpenOCD as a standalone programmer. The only required parameter is @option{filename}, the others are optional. @xref{Flash Programming}. @@ -6349,6 +6363,10 @@ works only for chips that do not have factory pre-programmed region 0 code. @end deffn +@deffn Command {nrf5 info} +Decodes and shows informations from FICR and UICR registers. +@end deffn + @end deffn @deffn {Flash Driver} ocl @@ -6751,6 +6769,37 @@ The @var{num} parameter is a value shown by @command{flash banks}. Mass erases the entire stm32h7x device. The @var{num} parameter is a value shown by @command{flash banks}. @end deffn + +@deffn Command {stm32h7x option_read} num reg_offset +Reads an option byte register from the stm32h7x device. +The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset} +is the register offset of the option byte to read from the used bank registers' base. +For example: in STM32H74x/H75x the bank 1 registers' base is 0x52002000 and 0x52002100 for bank 2. + +Example usage: +@example +# read OPTSR_CUR +stm32h7x option_read 0 0x1c +# read WPSN_CUR1R +stm32h7x option_read 0 0x38 +# read WPSN_CUR2R +stm32h7x option_read 1 0x38 +@end example +@end deffn + +@deffn Command {stm32h7x option_write} num reg_offset value [reg_mask] +Writes an option byte register of the stm32h7x device. +The @var{num} parameter is a value shown by @command{flash banks}, @var{reg_offset} +is the register offset of the option byte to write from the used bank register base, +and @var{reg_mask} is the mask to apply when writing the register (only bits with a '1' +will be touched). + +Example usage: +@example +# swap bank 1 and bank 2 in dual bank devices, by setting SWAP_BANK_OPT bit in OPTSR_PRG +stm32h7x option_write 0 0x20 0x8000000 0x8000000 +@end example +@end deffn @end deffn @deffn {Flash Driver} stm32lx @@ -7002,6 +7051,23 @@ unlock str9 device. @end deffn +@deffn {Flash Driver} swm050 +@cindex swm050 +All members of the swm050 microcontroller family from Foshan Synwit Tech. + +@example +flash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME +@end example + +One swm050-specific command is defined: + +@deffn Command {swm050 mass_erase} bank_id +Erases the entire flash bank. +@end deffn + +@end deffn + + @deffn {Flash Driver} tms470 Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores. @@ -7482,72 +7548,11 @@ or @code{read_page} methods, so @command{nand raw_access} won't change any behavior. @end deffn -@section mFlash - -@subsection mFlash Configuration -@cindex mFlash Configuration - -@deffn {Config Command} {mflash bank} soc base RST_pin target -Configures a mflash for @var{soc} host bank at -address @var{base}. -The pin number format depends on the host GPIO naming convention. -Currently, the mflash driver supports s3c2440 and pxa270. - -Example for s3c2440 mflash where @var{RST pin} is GPIO B1: - -@example -mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0 -@end example - -Example for pxa270 mflash where @var{RST pin} is GPIO 43: - -@example -mflash bank $_FLASHNAME pxa270 0x08000000 43 0 -@end example -@end deffn - -@subsection mFlash commands -@cindex mFlash commands - -@deffn Command {mflash config pll} frequency -Configure mflash PLL. -The @var{frequency} is the mflash input frequency, in Hz. -Issuing this command will erase mflash's whole internal nand and write new pll. -After this command, mflash needs power-on-reset for normal operation. -If pll was newly configured, storage and boot(optional) info also need to be update. -@end deffn - -@deffn Command {mflash config boot} -Configure bootable option. -If bootable option is set, mflash offer the first 8 sectors -(4kB) for boot. -@end deffn - -@deffn Command {mflash config storage} -Configure storage information. -For the normal storage operation, this information must be -written. -@end deffn - -@deffn Command {mflash dump} num filename offset size -Dump @var{size} bytes, starting at @var{offset} bytes from the -beginning of the bank @var{num}, to the file named @var{filename}. -@end deffn - -@deffn Command {mflash probe} -Probe mflash. -@end deffn - -@deffn Command {mflash write} num filename offset -Write the binary file @var{filename} to mflash bank @var{num}, starting at -@var{offset} bytes from the beginning of the bank. -@end deffn - @node Flash Programming @chapter Flash Programming OpenOCD implements numerous ways to program the target flash, whether internal or external. -Programming can be achieved by either using GDB @ref{programmingusinggdb,,Programming using GDB}, +Programming can be achieved by either using @ref{programmingusinggdb,,Programming using GDB}, or using the commands given in @ref{flashprogrammingcommands,,Flash Programming Commands}. @*To simplify using the flash commands directly a jimtcl script is available that handles the programming and verify stage. @@ -7558,6 +7563,7 @@ The script is executed as follows and by default the following actions will be p @item 'init' is executed. @item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed. @item @code{flash write_image} is called to erase and write any flash using the filename given. +@item If the @option{preverify} parameter is given, the target is "verified" first and only flashed if this fails. @item @code{verify_image} is called if @option{verify} parameter is given. @item @code{reset run} is called if @option{reset} parameter is given. @item OpenOCD is shutdown if @option{exit} parameter is given. @@ -8430,6 +8436,15 @@ Write @var{value} to the CTI register with the symbolic name @var{reg_name}. Print the value read from the CTI register with the symbolic name @var{reg_name}. @end deffn +@deffn Command {$cti_name ack} @var{event} +Acknowledge a CTI @var{event}. +@end deffn + +@deffn Command {$cti_name channel} @var{channel_number} @var{operation} +Perform a specific channel operation, the possible operations are: +gate, ungate, set, clear and pulse +@end deffn + @deffn Command {$cti_name testmode} @option{on|off} Enable (@option{on}) or disable (@option{off}) the integration test mode of the CTI.