X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=14835a919cb292d22e898d95d7d3950114abf75c;hp=21141caae6b25723b4cfd90c6ae84925fd8315ba;hb=751e2454bf076708d3e695833c4def460ab41d8b;hpb=d28ab08cfafb3ad7ff8dc539644883217e89f8c4 diff --git a/doc/openocd.texi b/doc/openocd.texi index 21141caae6..14835a919c 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -700,6 +700,7 @@ Configuration files and scripts are searched for in @item any search dir specified on the command line using the @option{-s} option, @item any search dir specified using the @command{add_script_search_dir} command, @item @file{$HOME/.openocd} (not on Windows), +@item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set), @item the site wide script library @file{$pkgdatadir/site} and @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}. @end enumerate @@ -2126,6 +2127,11 @@ The GDB port for the first target will be the base port, the second target will listen on gdb_port + 1, and so on. When not specified during the configuration stage, the port @var{number} defaults to 3333. + +Note: when using "gdb_port pipe", increasing the default remote timeout in +gdb (with 'set remotetimeout') is recommended. An insufficient timeout may +cause initialization to fail with "Unknown remote qXfer reply: OK". + @end deffn @deffn {Command} tcl_port [number] @@ -4927,6 +4933,9 @@ flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME @anchor{at91samd} @deffn {Flash Driver} at91samd @cindex at91samd +All members of the ATSAMD, ATSAMR, ATSAML and ATSAMC microcontroller +families from Atmel include internal flash and use ARM's Cortex-M0+ core. +This driver uses the same cmd names/syntax as @xref{at91sam3}. @deffn Command {at91samd chip-erase} Issues a complete Flash erase via the Device Service Unit (DSU). This can be @@ -4974,6 +4983,12 @@ at91samd bootloader 16384 @end example @end deffn +@deffn Command {at91samd dsu_reset_deassert} +This command releases internal reset held by DSU +and prepares reset vector catch in case of reset halt. +Command is used internally in event event reset-deassert-post. +@end deffn + @end deffn @anchor{at91sam3} @@ -5062,6 +5077,13 @@ Command is used internally in event event reset-deassert-post. @end deffn @end deffn +@deffn {Flash Driver} atsamv +@cindex atsamv +All members of the ATSAMV, ATSAMS, and ATSAME families from +Atmel include internal flash and use ARM's Cortex-M7 core. +This driver uses the same cmd names/syntax as @xref{at91sam3}. +@end deffn + @deffn {Flash Driver} at91sam7 All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores. The driver automatically @@ -5127,6 +5149,19 @@ flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME supported.} @end deffn +@deffn {Flash Driver} fm3 +All members of the FM3 microcontroller family from Fujitsu +include internal flash and use ARM Cortex M3 cores. +The @var{fm3} driver uses the @var{target} parameter to select the +correct bank config, it can currently be one of the following: +@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu}, +@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}. + +@example +flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME +@end example +@end deffn + @deffn {Flash Driver} lpc2000 This is the driver to support internal flash of all members of the LPC11(x)00 and LPC1300 microcontroller families and most members of @@ -5317,6 +5352,53 @@ lpc2900 secure_jtag 0 @end deffn @end deffn +@deffn {Flash Driver} mdr +This drivers handles the integrated NOR flash on Milandr Cortex-M +based controllers. A known limitation is that the Info memory can't be +read or verified as it's not memory mapped. + +@example +flash bank mdr \ + 0 0 @var{type} @var{page_count} @var{sec_count} +@end example + +@itemize @bullet +@item @var{type} - 0 for main memory, 1 for info memory +@item @var{page_count} - total number of pages +@item @var{sec_count} - number of sector per page count +@end itemize + +Example usage: +@example +if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{ + flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \ + 0 0 $_TARGETNAME 1 1 4 +@} else @{ + flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \ + 0 0 $_TARGETNAME 0 32 4 +@} +@end example +@end deffn + +@deffn {Flash Driver} nrf51 +All members of the nRF51 microcontroller families from Nordic Semiconductor +include internal flash and use ARM Cortex-M0 core. + +@example +flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME +@end example + +Some nrf51-specific commands are defined: + +@deffn Command {nrf51 mass_erase} +Erases the contents of the code memory and user information +configuration registers as well. It must be noted that this command +works only for chips that do not have factory pre-programmed region 0 +code. +@end deffn + +@end deffn + @deffn {Flash Driver} ocl This driver is an implementation of the ``on chip flash loader'' protocol proposed by Pavel Chromy. @@ -5389,6 +5471,29 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @end deffn +@deffn {Flash Driver} sim3x +All members of the SiM3 microcontroller family from Silicon Laboratories +include internal flash and use ARM Cortex M3 cores. It supports both JTAG +and SWD interface. +The @var{sim3x} driver tries to probe the device to auto detect the MCU. +If this failes, it will use the @var{size} parameter as the size of flash bank. + +@example +flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME +@end example + +There are 2 commands defined in the @var{sim3x} driver: + +@deffn Command {sim3x mass_erase} +Erases the complete flash. This is used to unlock the flash. +And this command is only possible when using the SWD interface. +@end deffn + +@deffn Command {sim3x lock} +Lock the flash. To unlock use the @command{sim3x mass_erase} command. +@end deffn +@end deffn + @deffn {Flash Driver} stellaris All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller families from Texas Instruments include internal flash. The driver @@ -5681,87 +5786,20 @@ the flash clock. @end deffn @end deffn -@deffn {Flash Driver} fm3 -All members of the FM3 microcontroller family from Fujitsu -include internal flash and use ARM Cortex M3 cores. -The @var{fm3} driver uses the @var{target} parameter to select the -correct bank config, it can currently be one of the following: -@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu}, -@code{mb9bfxx4.cpu}, @code{mb9bfxx5.cpu} or @code{mb9bfxx6.cpu}. - -@example -flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME -@end example -@end deffn - -@deffn {Flash Driver} sim3x -All members of the SiM3 microcontroller family from Silicon Laboratories -include internal flash and use ARM Cortex M3 cores. It supports both JTAG -and SWD interface. -The @var{sim3x} driver tries to probe the device to auto detect the MCU. -If this failes, it will use the @var{size} parameter as the size of flash bank. - -@example -flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME -@end example - -There are 2 commands defined in the @var{sim3x} driver: - -@deffn Command {sim3x mass_erase} -Erases the complete flash. This is used to unlock the flash. -And this command is only possible when using the SWD interface. -@end deffn - -@deffn Command {sim3x lock} -Lock the flash. To unlock use the @command{sim3x mass_erase} command. -@end deffn -@end deffn - -@deffn {Flash Driver} nrf51 -All members of the nRF51 microcontroller families from Nordic Semiconductor -include internal flash and use ARM Cortex-M0 core. - -@example -flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME -@end example +@deffn {Flash Driver} xmc4xxx +All members of the XMC4xxx microcontroller family from Infineon. +This driver does not require the chip and bus width to be specified. -Some nrf51-specific commands are defined: +Some xmc4xxx-specific commands are defined: -@deffn Command {nrf51 mass_erase} -Erases the contents of the code memory and user information -configuration registers as well. It must be noted that this command -works only for chips that do not have factory pre-programmed region 0 -code. +@deffn Command {xmc4xxx flash_password} bank_id passwd1 passwd2 +Saves flash protection passwords which are used to lock the user flash @end deffn +@deffn Command {xmc4xxx flash_unprotect} bank_id user_level[0-1] +Removes Flash write protection from the selected user bank @end deffn -@deffn {Flash Driver} mdr -This drivers handles the integrated NOR flash on Milandr Cortex-M -based controllers. A known limitation is that the Info memory can't be -read or verified as it's not memory mapped. - -@example -flash bank mdr \ - 0 0 @var{type} @var{page_count} @var{sec_count} -@end example - -@itemize @bullet -@item @var{type} - 0 for main memory, 1 for info memory -@item @var{page_count} - total number of pages -@item @var{sec_count} - number of sector per page count -@end itemize - -Example usage: -@example -if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{ - flash bank $@{_CHIPNAME@}_info.flash mdr 0x00000000 0x01000 \ - 0 0 $_TARGETNAME 1 1 4 -@} else @{ - flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 \ - 0 0 $_TARGETNAME 0 32 4 -@} -@end example @end deffn @section NAND Flash Commands @@ -7562,6 +7600,58 @@ fix CSW_SPROT from register AP_REG_CSW on selected dap. Defaulting to 0. @end deffn +@deffn Command {dap ti_be_32_quirks} [@option{enable}] +Set/get quirks mode for TI TMS450/TMS570 processors +Disabled by default +@end deffn + + +@subsection ARMv7-A specific commands +@cindex Cortex-A + +@deffn Command {cortex_a cache_info} +display information about target caches +@end deffn + +@deffn Command {cortex_a dbginit} +Initialize core debug +Enables debug by unlocking the Software Lock and clearing sticky powerdown indications +@end deffn + +@deffn Command {cortex_a smp_off} +Disable SMP mode +@end deffn + +@deffn Command {cortex_a smp_on} +Enable SMP mode +@end deffn + +@deffn Command {cortex_a smp_gdb} [core_id] +Display/set the current core displayed in GDB +@end deffn + +@deffn Command {cortex_a maskisr} [@option{on}|@option{off}] +Selects whether interrupts will be processed when single stepping +@end deffn + +@deffn Command {cache_config l2x} [base way] +configure l2x cache +@end deffn + + +@subsection ARMv7-R specific commands +@cindex Cortex-R + +@deffn Command {cortex_r dbginit} +Initialize core debug +Enables debug by unlocking the Software Lock and clearing sticky powerdown indications +@end deffn + +@deffn Command {cortex_r maskisr} [@option{on}|@option{off}] +Selects whether interrupts will be processed when single stepping +@end deffn + + @subsection ARMv7-M specific commands @cindex tracing @cindex SWO