X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;fp=doc%2Fopenocd.texi;h=f5852cc09eb02d164e678b4340967c0981f1cf80;hp=027e6d2edbb9d915b7e41da99d989d0a1bb20872;hb=487710da6d65e1704f68849a152fec76752d4f4e;hpb=1f4596cc46c96471f32d81613a612a4adefe36ab

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 027e6d2edb..f5852cc09e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4367,6 +4367,7 @@ compact Thumb2 instruction set.
 The current implementation supports eSi-32xx cores.
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
+@item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs.
 @item @code{mips_m4k} -- a MIPS core
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type. It is based on the ARMv5 architecture.