X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=NEWS;h=498797b1f4855cd5732f8789330890c487179155;hp=c5811bce5b35545f0e11acde904f49749714abdf;hb=a0edb8a328ceea23186ab74c941454fb146c9a48;hpb=83568b6b62b3508f10aa3a51fe4ae86421ec5d27

diff --git a/NEWS b/NEWS
index c5811bce5b..498797b1f4 100644
--- a/NEWS
+++ b/NEWS
@@ -8,20 +8,28 @@ JTAG Layer:
 
 Boundary Scan:
 Target Layer:
+	General
+		- new "reset-assert" event, for systems without SRST
 	ARM
 		- renamed "armv4_5" command prefix as "arm"
 		- recognize TrustZone "Secure Monitor" mode
 		- "arm regs" command output changed
 		- register names use "sp" not "r13"
+		- add top-level "mcr" and "mrc" commands, replacing
+		  various core-specific operations
+		- basic semihosting support
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
 		- accelerated GDB memory checksum
 		- support "arm regs" command
 		- can access all core modes and registers
+		- watchpoint support
 	Cortex-A8
 		- support "arm regs" command
 		- can access all core modes and registers
+		- supports "reset-assert" event (used on OMAP3530)
+		- watchpoint support
 	Cortex-M3
 		- Exposed DWT registers like cycle counter