Ensure that DaVinci chips can't start with a too-fast JTAG clock.

[openocd.git] / tcl / target / ti_dm6446.cfg

diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index 289518b790e43645fed31860b86ab1b23e380b32..cc23ad440c2e795b731817a50d99d4bf813ce68f 100644 (file)
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -68,6 +68,12 @@ set _TARGETNAME $_CHIPNAME.arm
 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable