tcl/target: start using the new TPIU/SWO support

[openocd.git] / tcl / target / stm32mp15x.cfg

diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index 4a8bc866c767ae341552ba580ebf60a0de6ac5a5..1b2ae7d5e71143797ba0a0bfe88c629620e6d1c7 100644 (file)
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -64,6 +64,9 @@ cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D800
 cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
 cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
 
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
+
 # interface does not work while srst is asserted
 # this is target specific, valid for every board
 # Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
@@ -108,9 +111,13 @@ proc detect_cpu1 {} {
        if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
 }
 
+proc rcc_enable_traceclk {} {
+       $::_CHIPNAME.ap2 mww 0x5000080c 0x301
+}
+
 # FIXME: most of handler below will be removed once reset framework get merged
 $_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
 $_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
@@ -118,4 +125,4 @@ $_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_exami
 $_CHIPNAME.ap1  configure -event examine-start       {dap init}
 $_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
 $_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}