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target/stm32h7x: add support of dual core variant of STM32H7
[openocd.git] / tcl / target / stm32h7x.cfg
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index ef9e29ac7db319f18f23911bbe08e42cc8f92d91..1d116542a7ddc45a6f64d417be277ed6eaac7a46 100644 (file)
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -12,6 +12,39 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME stm32h7x
 }
 
+if { [info exists DUAL_BANK] } {
+       set $_CHIPNAME.DUAL_BANK $DUAL_BANK
+       unset DUAL_BANK
+} else {
+       set $_CHIPNAME.DUAL_BANK 0
+}
+
+if { [info exists DUAL_CORE] } {
+       set $_CHIPNAME.DUAL_CORE $DUAL_CORE
+       unset DUAL_CORE
+} else {
+       set $_CHIPNAME.DUAL_CORE 0
+}
+
+# Issue a warning when hla is used, and fallback to single core configuration
+if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
+       echo "Warning : hla does not support multicore debugging"
+       set $_CHIPNAME.DUAL_CORE 0
+}
+
+if { [info exists USE_CTI] } {
+       set $_CHIPNAME.USE_CTI $USE_CTI
+       unset USE_CTI
+} else {
+       set $_CHIPNAME.USE_CTI 0
+}
+
+# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
+if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
+       echo "Warning : could not use CTI with a single core device, CTI is disabled"
+       set $_CHIPNAME.USE_CTI 0
+}
+
 set _ENDIAN little
 
 # Work-area is a space in RAM used for flash programming
@@ -46,13 +79,30 @@ if {![using_hla]} {
        target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
 }
 
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
 
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
+
+if {[set $_CHIPNAME.DUAL_BANK]} {
+       flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
+}
+
+if {[set $_CHIPNAME.DUAL_CORE]} {
+       target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
+
+       $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+       flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
+
+       if {[set $_CHIPNAME.DUAL_BANK]} {
+               flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
+       }
+}
+
+# Make sure that cpu0 is selected
+targets $_CHIPNAME.cpu0
 
 # Clock after reset is HSI at 64 MHz, no need of PLL
 adapter_khz 1800
@@ -78,7 +128,11 @@ reset_config srst_only srst_nogate
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
-   cortex_m reset_config sysresetreq
+       $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
+
+       if {[set $_CHIPNAME.DUAL_CORE]} {
+               $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
+       }
 
    # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
    # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
@@ -89,34 +143,56 @@ if {![using_hla]} {
    $_CHIPNAME.dap apcsw 0x08000000 0x08000000
 }
 
-$_TARGETNAME configure -event examine-end {
+$_CHIPNAME.cpu0 configure -event examine-end {
        # Enable D3 and D1 DBG clocks
        # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
        stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
        # Enable debug during low power modes (uses more power)
-       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
-       stm32h7x_dbgmcu_mmw 0x004 0x00000187 0
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
+       stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
 
        # Stop watchdog counters during halt
        # DBGMCU_APB3FZ1 |= WWDG1
        stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
-       # DBGMCU_APB4FZ1 |= WDGLSD1
-       stm32h7x_dbgmcu_mmw 0x054 0x00040000 0
+       # DBGMCU_APB1LFZ1 |= WWDG2
+       stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
+       # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
+       stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
 }
 
-$_TARGETNAME configure -event trace-config {
+$_CHIPNAME.cpu0 configure -event trace-config {
        # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
        # change this value accordingly to configure trace pins
        # assignment
        stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
 }
 
-$_TARGETNAME configure -event reset-init {
+$_CHIPNAME.cpu0 configure -event reset-init {
        # Clock after reset is HSI at 64 MHz, no need of PLL
        adapter_khz 4000
 }
 
+if {[set $_CHIPNAME.DUAL_CORE]} {
+       $_CHIPNAME.cpu1 configure -event examine-end {
+               # get _CHIPNAME from the current target
+               set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+               global $_CHIPNAME.USE_CTI
+
+               # Stop watchdog counters during halt
+               # DBGMCU_APB3FZ2 |= WWDG1
+               stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
+               # DBGMCU_APB1LFZ2 |= WWDG2
+               stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
+               # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
+               stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
+
+               if {[set $_CHIPNAME.USE_CTI]} {
+                       stm32h7x_cti_start
+               }
+       }
+}
+
 # like mrw, but with target selection
 proc stm32h7x_mrw {used_target reg} {
        set value ""
@@ -147,3 +223,53 @@ proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
 
        stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
 }
+
+if {[set $_CHIPNAME.USE_CTI]} {
+       # create CTI instances for both cores
+       cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
+       cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
+
+       $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
+       $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
+
+       $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+       $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
+
+       proc stm32h7x_cti_start {} {
+               # get _CHIPNAME from the current target
+               set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+               # Configure Cores' CTIs to halt each other
+               # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
+               $_CHIPNAME.cti0 write INEN0 0x1
+               $_CHIPNAME.cti0 write OUTEN0 0x1
+               $_CHIPNAME.cti1 write INEN0 0x1
+               $_CHIPNAME.cti1 write OUTEN0 0x1
+
+               # enable CTIs
+               $_CHIPNAME.cti0 enable on
+               $_CHIPNAME.cti1 enable on
+       }
+
+       proc stm32h7x_cti_stop {} {
+               # get _CHIPNAME from the current target
+               set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+               $_CHIPNAME.cti0 enable off
+               $_CHIPNAME.cti1 enable off
+       }
+
+       proc stm32h7x_cti_prepare_restart_all {} {
+               stm32h7x_cti_prepare_restart cti0
+               stm32h7x_cti_prepare_restart cti1
+       }
+
+       proc stm32h7x_cti_prepare_restart {cti} {
+               # get _CHIPNAME from the current target
+               set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
+
+               # Acknowlodge EDBGRQ at TRIGOUT0
+               $_CHIPNAME.$cti write INACK 0x01
+               $_CHIPNAME.$cti write INACK 0x00
+       }
+}
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