cfg: add stm32 cmsis-dap compliant config

[openocd.git] / tcl / target / stm32f3x.cfg

diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index d092b6c887cd565260eb774cd84fc7f595d207b4..3d68c4bfbafe657d5453fbb8edb0bf2c58001a83 100644 (file)
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -1,5 +1,10 @@
 # script for stm32f3x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,7 +34,9 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
@@ -39,7 +46,8 @@ if { [info exists CPUTAPID] } {
   # Section 29.6.3 - corresponds to Cortex-M4 r0p1
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
@@ -49,7 +57,10 @@ if { [info exists BSTAPID] } {
   set _BSTAPID1 0x06422041
   set _BSTAPID2 0x06432041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME