target: rename cortex_a8 to cortex_a

[openocd.git] / tcl / target / omap4430.cfg

diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg
index 19b2d70774008fab8948954ec31dc271ba71d7d2..6f3525aed78856c10e1fd0c134160f29713a6271 100644 (file)
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/omap4430.cfg
@@ -16,7 +16,7 @@ source [find target/icepick.cfg]
 #
 # A9 DAP
 #
-if { [info exists DAP_TAPID ] } {
+if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
 } else {
        set _DAP_TAPID 0x3BA00477
@@ -31,7 +31,7 @@ jtag configure $_CHIPNAME.dap -event tap-enable \
 #
 # M3 DAPs, one per core
 #
-if { [info exists M3_DAP_TAPID ] } {
+if { [info exists M3_DAP_TAPID] } {
        set _M3_DAP_TAPID $M3_DAP_TAPID
 } else {
        set _M3_DAP_TAPID 0x4BA00477
@@ -51,7 +51,7 @@ jtag configure $_CHIPNAME.m30_dap -event tap-enable \
 #
 # ICEpick-D JRC (JTAG route controller)
 #
-if { [info exists JRC_TAPID ] } {
+if { [info exists JRC_TAPID] } {
        set _JRC_TAPID $JRC_TAPID
 } else {
        set _JRC_TAPID  0x3b95c02f
@@ -59,7 +59,7 @@ if { [info exists JRC_TAPID ] } {
 }
 
 # PandaBoard REV EA1 (PEAP platforms)
-if { [info exists JRC_TAPID2 ] } {
+if { [info exists JRC_TAPID2] } {
        set _JRC_TAPID2 $JRC_TAPID2
 } else {
        set _JRC_TAPID2 0x1b85202f
@@ -68,7 +68,7 @@ if { [info exists JRC_TAPID2 ] } {
 
 
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-       -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2  
+       -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
 
 # Required by ICEpick to power-up the debug domain
 jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
@@ -82,7 +82,20 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
 # second core.
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a9 -chain-position $_CHIPNAME.dap -coreid 0
+
+# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
+# 0x80000000 is cpu0 coresight region
+#
+#
+# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
+# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
+
+set _coreid 0
+set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
+echo "Using dbgbase = [format 0x%x $_dbgbase]"
+ 
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
+  -coreid 0 -dbgbase $_dbgbase
 
 # SRAM: 56KiB at 0x4030.0000
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
@@ -91,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
 #
 # M3 targets, separate TAP/DAP for each core
 #
-target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap
+target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
+target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
 
 
 # Once the JRC is up, enable our TAPs
@@ -109,3 +122,6 @@ $_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0
 $_CHIPNAME.m30 configure -event reset-assert { }
 $_CHIPNAME.m31 configure -event reset-assert { }
 
+# Soft breakpoints don't currently work due to broken cache handling
+gdb_breakpoint_override hard
+