omap3530.cfg: use new "reset-assert" event

[openocd.git] / tcl / target / omap3530.cfg

diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 45f3c01ce59dd6493b39c69e11ef12e6adb1e97b..74edd7289fbdf8b5f89cad2fc4e92c04bf58305b 100644 (file)
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -38,6 +38,9 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
 
+# SRAM: 64K at 0x4020.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
 ###################
 
 # the reset sequence is event-driven
@@ -62,10 +65,10 @@ proc omap3_dbginit {target} {
 jtag_rclk 1000
 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
 
-# REVISIT This assumes that SRST is unavailable, so we must assert reset
+# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
 # ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick
 # would issue.  RST_DPLL3 (4) is a cold reset.
 set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
+$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
 
 $_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"