Fix spelling of ARM Cortex

[openocd.git] / tcl / target / lpc1xxx.cfg

diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg
index 226425d41f3cf1225d7f496cdc2ea87619fa17b1..9c10e9f933a3bc1633e22e611d7dfa08a86131ca 100644 (file)
--- a/tcl/target/lpc1xxx.cfg
+++ b/tcl/target/lpc1xxx.cfg
@@ -56,7 +56,7 @@ if { [info exists CPUTAPID] } {
        # Allow user override
        set _CPUTAPID $CPUTAPID
 } else {
-       # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
+       # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
        if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
                set _CPUTAPID 0x0bb11477
        } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
@@ -148,10 +148,10 @@ if {[using_jtag]} {
  jtag_ntrst_delay 200
 }
 
-# LPC8xx (Cortex M0+ core) support SYSRESETREQ
-# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
-# LPC40xx (Cortex M4F core) support SYSRESETREQ
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
 if {![using_hla]} {
     # if srst is not fitted use SYSRESETREQ to
     # perform a soft reset