at91samd: handle reset run/halt in DSU

[openocd.git] / tcl / target / at91samdXX.cfg

diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg
index fb3be04a4b35b568a470abacb6ea6382295b0429..50d93f59035a367a7f8275d83e020443bac760ca 100644 (file)
--- a/tcl/target/at91samdXX.cfg
+++ b/tcl/target/at91samdXX.cfg
@@ -1,5 +1,5 @@
 #
-# script for ATMEL samdXX, a CORTEX-M0 chip
+# script for Atmel SAMD, SAMR, SAML or SAMC, a CORTEX-M0 chip
 #
 
 #
@@ -40,15 +40,42 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAM
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
 #
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
+# dsu_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the DSU to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post {
+        at91samd dsu_reset_deassert
+}
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) cannot
+# stop the MCU before it starts executing code if hardware RESETN
+# line is configured by command "reset_config srst_only"
+# Use "reset_config none" (default) before flash programming.
+
+# Do not use a reset button with other SWD adapter than Atmel's EDBG.
+# DSU usually locks MCU in reset state until you issue a reset command
+# in OpenOCD.
+
+# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
+# Other members of family usually use SYSCLK = 4 MHz after reset.
+# Datasheet does not specify SYSCLK to SWD clock ratio.
+# Usually used SYSCLK/6 is slow, testing shows that debugging can
+# work @ SYSCLK/2 but your mileage may vary.
+# This limit is most probably imposed by incorrectly handled SWD WAIT
+# on some SWD adapters.
+
+adapter_khz 400
 
-adapter_khz 500
-adapter_nsrst_delay 100
+# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
+# without problem at maximal clock speed. Atmel recommends
+# adapter speed less than 10 * CPU clock.
+# adapter_khz 5000
 
 if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to