at91: add chip register definition and generic init support

[openocd.git] / tcl / chip / atmel / at91 / at91_pmc.cfg

diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
new file mode 100644 (file)
index 0000000..88b1370
--- /dev/null
+++ b/tcl/chip/atmel/at91/at91_pmc.cfg
@@ -0,0 +1,113 @@
+set    AT91_PMC_SCER           [expr ($AT91_PMC + 0x00)]       ;# System Clock Enable Register
+set    AT91_PMC_SCDR           [expr ($AT91_PMC + 0x04)]       ;# System Clock Disable Register
+
+set    AT91_PMC_SCSR           [expr ($AT91_PMC + 0x08)]       ;# System Clock Status Register
+set            AT91_PMC_PCK            [expr (1 <<  0)]                ;# Processor Clock
+set            AT91RM9200_PMC_UDP      [expr (1 <<  1)]                ;# USB Devcice Port Clock [AT91RM9200 only]
+set            AT91RM9200_PMC_MCKUDP   [expr (1 <<  2)]                ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set            AT91CAP9_PMC_DDR        [expr (1 <<  2)]                ;# DDR Clock [CAP9 revC & some SAM9 only]
+set            AT91RM9200_PMC_UHP      [expr (1 <<  4)]                ;# USB Host Port Clock [AT91RM9200 only]
+set            AT91SAM926x_PMC_UHP     [expr (1 <<  6)]                ;# USB Host Port Clock [AT91SAM926x only]
+set            AT91CAP9_PMC_UHP        [expr (1 <<  6)]                ;# USB Host Port Clock [AT91CAP9 only]
+set            AT91SAM926x_PMC_UDP     [expr (1 <<  7)]                ;# USB Devcice Port Clock [AT91SAM926x only]
+set            AT91_PMC_PCK0           [expr (1 <<  8)]                ;# Programmable Clock 0
+set            AT91_PMC_PCK1           [expr (1 <<  9)]                ;# Programmable Clock 1
+set            AT91_PMC_PCK2           [expr (1 << 10)]                ;# Programmable Clock 2
+set            AT91_PMC_PCK3           [expr (1 << 11)]                ;# Programmable Clock 3
+set            AT91_PMC_HCK0           [expr (1 << 16)]                ;# AHB Clock (USB host) [AT91SAM9261 only]
+set            AT91_PMC_HCK1           [expr (1 << 17)]                ;# AHB Clock (LCD) [AT91SAM9261 only]
+
+set    AT91_PMC_PCER           [expr ($AT91_PMC + 0x10)]       ;# Peripheral Clock Enable Register
+set    AT91_PMC_PCDR           [expr ($AT91_PMC + 0x14)]       ;# Peripheral Clock Disable Register
+set    AT91_PMC_PCSR           [expr ($AT91_PMC + 0x18)]       ;# Peripheral Clock Status Register
+
+set    AT91_CKGR_UCKR          [expr ($AT91_PMC + 0x1C)]       ;# UTMI Clock Register [some SAM9, CAP9]
+set            AT91_PMC_UPLLEN         [expr (1   << 16)]              ;# UTMI PLL Enable
+set            AT91_PMC_UPLLCOUNT      [expr (0xf << 20)]              ;# UTMI PLL Start-up Time
+set            AT91_PMC_BIASEN         [expr (1   << 24)]              ;# UTMI BIAS Enable
+set            AT91_PMC_BIASCOUNT      [expr (0xf << 28)]              ;# UTMI BIAS Start-up Time
+
+set    AT91_CKGR_MOR           [expr ($AT91_PMC + 0x20)]       ;# Main Oscillator Register [not on SAM9RL]
+set            AT91_PMC_MOSCEN         [expr (1    << 0)]              ;# Main Oscillator Enable
+set            AT91_PMC_OSCBYPASS      [expr (1    << 1)]              ;# Oscillator Bypass [SAM9x, CAP9]
+set            AT91_PMC_OSCOUNT        [expr (0xff << 8)]              ;# Main Oscillator Start-up Time
+
+set    AT91_CKGR_MCFR          [expr ($AT91_PMC + 0x24)]       ;# Main Clock Frequency Register
+set            AT91_PMC_MAINF          [expr (0xffff <<  0)]           ;# Main Clock Frequency
+set            AT91_PMC_MAINRDY        [expr (1        << 16)]         ;# Main Clock Ready
+
+set    AT91_CKGR_PLLAR         [expr ($AT91_PMC + 0x28)]       ;# PLL A Register
+set    AT91_CKGR_PLLBR         [expr ($AT91_PMC + 0x2c)]       ;# PLL B Register
+set            AT91_PMC_DIV            [expr (0xff  <<  0)]            ;# Divider
+set            AT91_PMC_PLLCOUNT       [expr (0x3f  <<  8)]            ;# PLL Counter
+set            AT91_PMC_OUT            [expr (3     << 14)]            ;# PLL Clock Frequency Range
+set            AT91_PMC_MUL            [expr (0x7ff << 16)]            ;# PLL Multiplier
+set            AT91_PMC_USBDIV         [expr (3     << 28)]            ;# USB Divisor (PLLB only)
+set                    AT91_PMC_USBDIV_1               [expr (0 << 28)]
+set                    AT91_PMC_USBDIV_2               [expr (1 << 28)]
+set                    AT91_PMC_USBDIV_4               [expr (2 << 28)]
+set            AT91_PMC_USB96M         [expr (1     << 28)]            ;# Divider by 2 Enable (PLLB only)
+set            AT91_PMC_PLLA_WR_ERRATA [expr (1     << 29)]            ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+
+set    AT91_PMC_MCKR           [expr ($AT91_PMC + 0x30)]       ;# Master Clock Register
+set            AT91_PMC_CSS            [expr (3 <<  0)]                ;# Master Clock Selection
+set                    AT91_PMC_CSS_SLOW               [expr (0 << 0)]
+set                    AT91_PMC_CSS_MAIN               [expr (1 << 0)]
+set                    AT91_PMC_CSS_PLLA               [expr (2 << 0)]
+set                    AT91_PMC_CSS_PLLB               [expr (3 << 0)]
+set                    AT91_PMC_CSS_UPLL               [expr (3 << 0)] ;# [some SAM9 only]
+set            AT91_PMC_PRES           [expr (7 <<  2)]                ;# Master Clock Prescaler
+set                    AT91_PMC_PRES_1                 [expr (0 << 2)]
+set                    AT91_PMC_PRES_2                 [expr (1 << 2)]
+set                    AT91_PMC_PRES_4                 [expr (2 << 2)]
+set                    AT91_PMC_PRES_8                 [expr (3 << 2)]
+set                    AT91_PMC_PRES_16                [expr (4 << 2)]
+set                    AT91_PMC_PRES_32                [expr (5 << 2)]
+set                    AT91_PMC_PRES_64                [expr (6 << 2)]
+set            AT91_PMC_MDIV           [expr (3 <<  8)]                ;# Master Clock Division
+set                    AT91RM9200_PMC_MDIV_1           [expr (0 << 8)] ;# [AT91RM9200 only]
+set                    AT91RM9200_PMC_MDIV_2           [expr (1 << 8)]
+set                    AT91RM9200_PMC_MDIV_3           [expr (2 << 8)]
+set                    AT91RM9200_PMC_MDIV_4           [expr (3 << 8)]
+set                    AT91SAM9_PMC_MDIV_1             [expr (0 << 8)] ;# [SAM9,CAP9 only]
+set                    AT91SAM9_PMC_MDIV_2             [expr (1 << 8)]
+set                    AT91SAM9_PMC_MDIV_4             [expr (2 << 8)]
+set                    AT91SAM9_PMC_MDIV_6             [expr (3 << 8)] ;# [some SAM9 only]
+set                    AT91SAM9_PMC_MDIV_3             [expr (3 << 8)] ;# [some SAM9 only]
+set            AT91_PMC_PDIV           [expr (1 << 12)]                ;# Processor Clock Division [some SAM9 only]
+set                    AT91_PMC_PDIV_1                 [expr (0 << 12)]
+set                    AT91_PMC_PDIV_2                 [expr (1 << 12)]
+set            AT91_PMC_PLLADIV2       [expr (1 << 12)]                ;# PLLA divisor by 2 [some SAM9 only]
+set                    AT91_PMC_PLLADIV2_OFF           [expr (0 << 12)]
+set                    AT91_PMC_PLLADIV2_ON            [expr (1 << 12)]
+
+set    AT91_PMC_USB            [expr ($AT91_PMC + 0x38)]       ;# USB Clock Register [some SAM9 only]
+set            AT91_PMC_USBS           [expr (0x1 <<  0)]              ;# USB OHCI Input clock selection
+set                    AT91_PMC_USBS_PLLA              [expr (0 << 0)]
+set                    AT91_PMC_USBS_UPLL              [expr (1 << 0)]
+set            AT91_PMC_OHCIUSBDIV     [expr (0xF <<  8)]              ;# Divider for USB OHCI Clock
+
+;# set AT91_PMC_PCKR(n)        [expr ($AT91_PMC + 0x40 + ((n) * 4))]   ;# Programmable Clock 0-N Registers
+set            AT91_PMC_CSSMCK         [expr (0x1 <<  8)]              ;# CSS or Master Clock Selection
+set                    AT91_PMC_CSSMCK_CSS             [expr (0 << 8)]
+set                    AT91_PMC_CSSMCK_MCK             [expr (1 << 8)]
+
+set    AT91_PMC_IER            [expr ($AT91_PMC + 0x60)]       ;# Interrupt Enable Register
+set    AT91_PMC_IDR            [expr ($AT91_PMC + 0x64)]       ;# Interrupt Disable Register
+set    AT91_PMC_SR             [expr ($AT91_PMC + 0x68)]       ;# Status Register
+set            AT91_PMC_MOSCS          [expr (1 <<  0)]                ;# MOSCS Flag
+set            AT91_PMC_LOCKA          [expr (1 <<  1)]                ;# PLLA Lock
+set            AT91_PMC_LOCKB          [expr (1 <<  2)]                ;# PLLB Lock
+set            AT91_PMC_MCKRDY         [expr (1 <<  3)]                ;# Master Clock
+set            AT91_PMC_LOCKU          [expr (1 <<  6)]                ;# UPLL Lock [some SAM9, AT91CAP9 only]
+set            AT91_PMC_OSCSEL         [expr (1 <<  7)]                ;# Slow Clock Oscillator [AT91CAP9 revC only]
+set            AT91_PMC_PCK0RDY        [expr (1 <<  8)]                ;# Programmable Clock 0
+set            AT91_PMC_PCK1RDY        [expr (1 <<  9)]                ;# Programmable Clock 1
+set            AT91_PMC_PCK2RDY        [expr (1 << 10)]                ;# Programmable Clock 2
+set            AT91_PMC_PCK3RDY        [expr (1 << 11)]                ;# Programmable Clock 3
+set    AT91_PMC_IMR            [expr ($AT91_PMC + 0x6c)]       ;# Interrupt Mask Register
+
+set AT91_PMC_PROT              [expr ($AT91_PMC + 0xe4)]       ;# Protect Register [AT91CAP9 revC only]
+set            AT91_PMC_PROTKEY        0x504d4301      ;# Activation Code
+
+set AT91_PMC_VER               [expr ($AT91_PMC + 0xfc)]       ;# PMC Module Version [AT91CAP9 only]