Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface

[openocd.git] / tcl / board / stm32l4r9i-disco.cfg

diff --git a/tcl/board/stm32l4r9i-disco.cfg b/tcl/board/stm32l4r9i-disco.cfg
new file mode 100644 (file)
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+# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.
+# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set OCTOSPI1 1
+set OCTOSPI2 0
+
+source [find target/stm32l4x.cfg]
+
+# OCTOSPI initialization
+# octo: 8-line mode
+proc octospi_init { octo } {
+       global a b
+       mmw 0x4002104C 0x001001FF 0                             ;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)
+       mmw 0x40021050 0x00000300 0                             ;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)
+       mmw 0x40021058 0x10000000 0                             ;# RCC_APB1ENR1 |= PWREN (enable clock)
+       sleep 1                                                                 ;# Wait for clock startup
+
+       mmw 0x40007004 0x00000200 0                             ;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)
+
+       mww 0x50061C04 0x00000000                               ;# OCTOSPIM_P1CR: disable Port 1
+       mww 0x50061C08 0x03010111                               ;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1
+
+       # PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,
+       # PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0
+
+       # PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V
+       # PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+
+       # Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V
+       mmw 0x48001800 0x82280000 0x41140000    ;# MODER
+       mmw 0x48001808 0xC33C0000 0x00000000    ;# OSPEEDR
+       mmw 0x48001824 0x50050550 0xA00A0AA0    ;# AFRH
+
+       # Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V
+       mmw 0x48001C00 0x002A0000 0x00150000    ;# MODER
+       mmw 0x48001C08 0x003F0000 0x00000000    ;# OSPEEDR
+       mmw 0x48001C24 0x00000555 0x00000AAA    ;# AFRH
+
+       # Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V
+       mmw 0x48002000 0x00A82000 0x00541000    ;# MODER
+       mmw 0x48002008 0x00FC3000 0x00000000    ;# OSPEEDR
+       mmw 0x48002020 0x05000000 0x0A000000    ;# AFRL
+       mmw 0x48002024 0x00005550 0x0000AAA0    ;# AFRH
+
+       # OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
+       mww 0xA0001130 0x00001000                               ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+       mww 0xA0001000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
+       mww 0xA0001008 0x01190100                               ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
+       mww 0xA000100C 0x00000001                               ;# OCTOSPI_DCR2: PRESCALER=1
+
+       mww 0xA0001108 0x00000000                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
+       mww 0xA0001100 0x01003101                               ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
+       mww 0xA0001110 0x00000013                               ;# OCTOSPI_IR: INSTR=READ4B
+
+       if { $octo == 1 } {
+               stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+               stmqspi cmd $a 0 0x06                                                           ;# Write Enable
+               stmqspi cmd $a 1 0x05                                                           ;# Read Status Register
+               stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02          ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
+
+               # OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
+               mww 0xA0001000 0x3040000B                               ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
+               mww 0xA0001108 0x10000006                               ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
+               mww 0xA0001100 0x2C003C1C                               ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
+               mww 0xA0001110 0x0000EE11                               ;# OCTOSPI_IR: INSTR=OCTA DTR Read
+
+               flash probe $a                                                  ;# reload configuration from CR, TCR, CCR, IR register values
+
+               stmqspi cmd $a 0 0x06                                                           ;# Write Enable
+               stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
+               stmqspi cmd $a 0 0x04                                                           ;# Write Disable
+               stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00                       ;# Read Status Register (note dummy address in 8-line mode)
+               stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00                       ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
+       }
+}
+
+$_TARGETNAME configure -event reset-init {
+       mmw 0x40022000 0x00000003 0x0000000C    ;# 3 WS for 72 MHz HCLK
+       sleep 1
+       mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
+       mww 0x4002100C 0x01002432                               ;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+       mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
+       mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
+       sleep 1
+       mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
+       sleep 1
+
+       adapter speed 4000
+
+       octospi_init 1
+}